KR970053902A - 공정시간 단축형 반도체 제조방법 - Google Patents

공정시간 단축형 반도체 제조방법 Download PDF

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Publication number
KR970053902A
KR970053902A KR1019950068619A KR19950068619A KR970053902A KR 970053902 A KR970053902 A KR 970053902A KR 1019950068619 A KR1019950068619 A KR 1019950068619A KR 19950068619 A KR19950068619 A KR 19950068619A KR 970053902 A KR970053902 A KR 970053902A
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South Korea
Prior art keywords
nitride
nitride film
substrate
photolithography process
film
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Ceased
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KR1019950068619A
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English (en)
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구본열
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김광호
삼성전자 주식회사
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Priority to KR1019950068619A priority Critical patent/KR970053902A/ko
Priority to TW085108473A priority patent/TW297922B/zh
Priority to JP8235586A priority patent/JPH09191055A/ja
Priority to US08/748,193 priority patent/US5773336A/en
Publication of KR970053902A publication Critical patent/KR970053902A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0156—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H10W10/0127—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers using both n-type and p-type impurities, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 공정기간 단축형 반도체 제조방법에 관한 것으로서, 특히 반도체 기판 상에 산화막 및 제1질화막을 차례로 적층하는 단계; 사진 식각공정에 의해 제1전도형의 웰을 형성하기 위한 영역상의 상기 질화막을 선택적으로 식각하고 제1전도형의 불순물을 이온주입하는 단계; 사진 식각공정의 레지스터를 제거하고 기판의 전면에 제2질화막을 도포하는 단계; 사진 식각공정에 의해 액티브 영역상의 제1 및 제2질화막을 남기고 나머지 제1 및 제2질화막을 제거하는 단계; 사진 공정에 의해 선택적으로 필드 이온주입을 수행하는 단계; 필드 이온 주입후에 기판을 고온에서 열처리하여 필드 산화막을 성장시킴과 동시에 웰확산을 수행하는 단계; 및 액티브 영역상에 남겨진 제1 및 제2질화막을 제거하는 단계를 구비하는 것을 특징으로 한다.
따라서, 본 발명에서는 공정을 단순화시켜서 공정기간을 단축시킬 수 있어서 생산성을 향상시킬 수 있다.

Description

공정기간 단축형 반도체 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제11도 내지 제14도는 본 발명에 의한 공정기가 단축형 반도체 제조방법의 공정 순서를 나타낸 도면.

Claims (5)

  1. 반도체 기판 상에 산화막 및 제1질화막을 차례로 적층하는 단계; 사진 식각공정에 의해 제1전도형의 웰을 형성하기 위한 영역상의 상기 질화막을 선택적으로 식각하고 제1전도형의 불순물을 이온주입하는 단계; 상기 사진 식각공정의 레지스터를 제거하고 기판의 전면에 제2질화막을 도포하는 단계; 사진 식각공정에 의해 액티브 영역상의 제1 및 제2질화막을 남기고 나머지 제1 및 제2질화막을 제거하는 단계; 사진 공정에 의해 선택적으로 필드 이온주입을 수행하는 단계; 상기 필드 이온 주입후에 기판을 고온에서 열처리하여 필드 산화막을 성장시킴과 동시에 웰확산을 수행하는 단계; 및 상기 액티브 영역상에 남겨진 제1 및 제2질화막을 제거하는 단계를 구비하는 것을 특징으로 하는 공정기간 단축형 반도체 제조방법.
  2. 제1항에 있어서, 상기 열처리는 1000℃ 이상인 것을 특징으로 하는 공정기간 단축형 반도체 제조방법.
  3. 제1항에 있어서, 상기 제1산화막의 두께는 250Å인 것을 특징으로 하는 공정기간 단축형 반도체 제조방법.
  4. 제1항에 있어서, 상기 제1산화막의 두께는 500Å인 것을 특징으로 하는 공정기간 단축형 반도체 제조방법.
  5. 제1항에 있어서, 상기 제2질화막의 두께는 1500Å인 것을 특징으로 하는 공정기간 단축형 반도체 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950068619A 1995-12-30 1995-12-30 공정시간 단축형 반도체 제조방법 Ceased KR970053902A (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019950068619A KR970053902A (ko) 1995-12-30 1995-12-30 공정시간 단축형 반도체 제조방법
TW085108473A TW297922B (en) 1995-12-30 1996-07-12 Method for fabricating a semiconductor
JP8235586A JPH09191055A (ja) 1995-12-30 1996-09-05 工程期間短縮型の半導体製造方法
US08/748,193 US5773336A (en) 1995-12-30 1996-11-12 Methods of forming semiconductor active regions having channel-stop isolation regions therein

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950068619A KR970053902A (ko) 1995-12-30 1995-12-30 공정시간 단축형 반도체 제조방법

Publications (1)

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KR970053902A true KR970053902A (ko) 1997-07-31

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US (1) US5773336A (ko)
JP (1) JPH09191055A (ko)
KR (1) KR970053902A (ko)
TW (1) TW297922B (ko)

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JP3390319B2 (ja) * 1997-02-03 2003-03-24 シャープ株式会社 半導体装置及びその製造方法
US6071775A (en) * 1997-02-21 2000-06-06 Samsung Electronics Co., Ltd. Methods for forming peripheral circuits including high voltage transistors with LDD structures
US6190952B1 (en) * 1999-03-03 2001-02-20 Advanced Micro Devices, Inc. Multiple semiconductor-on-insulator threshold voltage circuit
US6200861B1 (en) * 1999-03-26 2001-03-13 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating high density multiple states mask ROM cells
US6455903B1 (en) 2000-01-26 2002-09-24 Advanced Micro Devices, Inc. Dual threshold voltage MOSFET by local confinement of channel depletion layer using inert ion implantation
US6586289B1 (en) * 2001-06-15 2003-07-01 International Business Machines Corporation Anti-spacer structure for improved gate activation

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JPS5522856A (en) * 1978-08-07 1980-02-18 Toshiba Corp Semiconductor device and its manufacturing method
JPS60106142A (ja) * 1983-11-15 1985-06-11 Nec Corp 半導体素子の製造方法
US4728619A (en) * 1987-06-19 1988-03-01 Motorola, Inc. Field implant process for CMOS using germanium
JPH01241142A (ja) * 1988-03-23 1989-09-26 Toshiba Corp 半導体装置の製造方法
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KR920001402B1 (ko) * 1988-11-29 1992-02-13 삼성전자 주식회사 불휘발성 반도체 기억소자
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TW297922B (en) 1997-02-11
JPH09191055A (ja) 1997-07-22
US5773336A (en) 1998-06-30

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