KR970077184A - 반도체소자의 콘택홀 형성방법 - Google Patents

반도체소자의 콘택홀 형성방법 Download PDF

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Publication number
KR970077184A
KR970077184A KR1019960014113A KR19960014113A KR970077184A KR 970077184 A KR970077184 A KR 970077184A KR 1019960014113 A KR1019960014113 A KR 1019960014113A KR 19960014113 A KR19960014113 A KR 19960014113A KR 970077184 A KR970077184 A KR 970077184A
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South Korea
Prior art keywords
gas
insulating film
forming
etching
contact hole
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KR1019960014113A
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KR100244793B1 (ko
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김정호
김진웅
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김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960014113A priority Critical patent/KR100244793B1/ko
Priority to US08/847,811 priority patent/US5869404A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체소자의 콘택홀 형성방법에 관한 것으로, 반도체기판 상부에 워드라인 및 제1내부절연막을 형성하고 상기 워드라인과 제1내부절연막 측벽에 절연막 스페이서를 형성한 다음, 전체표면상부에 제2내부절연막인 질화막을 일정두께 형성하고 그 상부를 평탄화시키는 평탄화층을 형성한 다음, 콘택마스크를 이용한 식각공정으로 상기 평탄화층을 식각하여 상기 제2내부절연막을 노출시키는 콘택홀을 형성하되, 종래의 C4F8와 Ar 가스에 수소를 함유하는 가스가 첨가된 식각가스를 이용하여 실시함으로써 종래의 평탄화층 식각공정시 발생되는 C-C계 폴리머보다 결합력이 약한 C-H계 플리머를 더 많이 발생시켜 식각멈춤현상을 방지하고 과도식각으로인한 하부층 손상을 방지하여 접합누설전류의 증가가 없는 콘택홀을 형성함으로써 반도체 소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.

Description

반도체소자의 콘택홀 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도 내지 제2D도는 본 발명의 실시예에 반도체소자의 콘택홀 형성방법을 도시한 단면도.

Claims (8)

  1. 반도체기판 상부에 워드라인 및 제1내부절연막을 형성하고 상기 워드라인과 제1내부절연막 측벽에 절연막 스페이서를 형성한 다음, 전체표면상부에 제2내부절연막인 질화막을 일정두께 형성하고 그 상부를 평탄화시키는 평탄화층을 형성한 다음, 콘택마스크를 이용한 식각공정으로 상기 평탄화층을 식각하여 상기 제2내부절연막을 노출시키는 콘택홀을 형성하는 반도체소자의 콘택홀 형성방법에 있어서, 상기 평탄화층 식각공정은 C4F8와 Ar 가스에 수소를 함유하는 가스가 첨가된 식각가스를 이용하여 실시하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.
  2. 제1항에 있어서, 상기 수소를 함유하는 가스는 CH3F 가스를 사용하는 것을 특징으로 하는 반도체 소자용 콘택홀 형성방법.
  3. 제1항에 있어서, 상기 수소를 함유하는 가스는 C2H2가스를 사용하는 것을 특징으로 하는 반도체 소자용 콘택홀 형성방법.
  4. 제1항에 있어서, 상기 수소를 함유하는 가스는 CH2F2가스를 사용하는 것을 특징으로 하는 반도체 소자용 콘택홀 형성방법.
  5. 제1항에 있어서, 상기 수소를 함유하는 가스는 CHF3가스를 사용하는 것을 특징으로 하는 반도체 소자용 콘택홀 형성방법.
  6. 제1항에 있어서, 상기 평탄화층 식각공정은 소오스파워 1000∼3000와트, 바이어스 파워 500∼2000와트, C4F8와 Ar 가스유량을 각각 5∼30 SCCM과 0∼500 SCCM으로 하고 수소를 함유하는 가스로 실시하는 것을 특징으로 하는 반도체 소자용 콘택홀 형성방법.
  7. 제1항 내지 제6항 중 어느 한 항에 있어서, 상기 수소를 함유하는 가수는 가스유량을 0∼30 SCCM으로 하여 실시하는 것을 특징으로 하는 반도체 소자용 콘택홀 형성방법.
  8. 제1항에 있어서, 상기 평탄화층 식각공정은 평탄화층과 제2내부절연막의 식각 선택비를 50∼200으로 하여 실시하는 것을 특징으로 하는 반도체 소자용 콘택홀 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960014113A 1996-05-01 1996-05-01 반도체 소자의 콘택홀 형성방법 Expired - Fee Related KR100244793B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019960014113A KR100244793B1 (ko) 1996-05-01 1996-05-01 반도체 소자의 콘택홀 형성방법
US08/847,811 US5869404A (en) 1996-05-01 1997-04-25 Method for forming contact hole of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960014113A KR100244793B1 (ko) 1996-05-01 1996-05-01 반도체 소자의 콘택홀 형성방법

Publications (2)

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KR970077184A true KR970077184A (ko) 1997-12-12
KR100244793B1 KR100244793B1 (ko) 2000-03-02

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US (1) US5869404A (ko)
KR (1) KR100244793B1 (ko)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297167B1 (en) * 1997-09-05 2001-10-02 Advanced Micro Devices, Inc. In-situ etch of multiple layers during formation of local interconnects
US5955380A (en) * 1997-09-30 1999-09-21 Siemens Aktiengesellschaft Endpoint detection method and apparatus
KR100311487B1 (ko) * 1997-12-16 2001-11-15 김영환 산화막식각방법
JP3722610B2 (ja) * 1998-01-14 2005-11-30 株式会社リコー 半導体装置の製造方法
US6025255A (en) * 1998-06-25 2000-02-15 Vanguard International Semiconductor Corporation Two-step etching process for forming self-aligned contacts
US6329292B1 (en) * 1998-07-09 2001-12-11 Applied Materials, Inc. Integrated self aligned contact etch
DE10154966A1 (de) * 2001-10-31 2003-05-22 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleitervorrichtung
KR100792386B1 (ko) * 2006-09-29 2008-01-09 주식회사 하이닉스반도체 반도체 소자의 제조 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0258221A (ja) * 1988-08-23 1990-02-27 Semiconductor Energy Lab Co Ltd 炭素または炭素を主成分とするマスクを用いたエッチング方法
JPH0383335A (ja) * 1989-08-28 1991-04-09 Hitachi Ltd エッチング方法
JP3092185B2 (ja) * 1990-07-30 2000-09-25 セイコーエプソン株式会社 半導体装置の製造方法
US5405491A (en) * 1994-03-04 1995-04-11 Motorola Inc. Plasma etching process
JPH08203998A (ja) * 1995-01-20 1996-08-09 Sony Corp 多層配線の形成方法

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US5869404A (en) 1999-02-09

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