KR970077224A - 폴리사이드 게이트 형성방법 - Google Patents

폴리사이드 게이트 형성방법 Download PDF

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KR970077224A
KR970077224A KR1019970016816A KR19970016816A KR970077224A KR 970077224 A KR970077224 A KR 970077224A KR 1019970016816 A KR1019970016816 A KR 1019970016816A KR 19970016816 A KR19970016816 A KR 19970016816A KR 970077224 A KR970077224 A KR 970077224A
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gas
etching
film
silicide
layer
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KR100265756B1 (ko
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신화숙
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윤종용
삼성전자 주식회사
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • H10D64/0132—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN the conductor being a metallic silicide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/01312—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition

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  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

측벽침해 현상을 최소화할 수 있는 폴리사이드 게이트의 형성방법에 대해 기재되어 있다. 이는, 반도체기판상에 게이트절연막, 폴리실리콘막 및 실리사이드막을 차례로 형성하는 단계와, 이 실리사이드막 상에 마스크층을 형성하는 단계, 염소가스(Cl2)와 산소가스(O2)의 혼합가스를 사용하여 실리사이드막 및 폴리실리콘막을 식각하는 단계로 이루어진다.

Description

폴리사이드 게이트 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도 내지 제5도는 본 발명의 방법에 의해 식각된 폴리사이드 게이트의 단면을 산소가스(O2)의 비율에 따라 관측한 SEM 사진들이다.

Claims (15)

  1. 반도체기판 상에 게이트절연막, 폴리실리콘막 및 실리사이드막을 차례로 형성하는 단계; 상기 실리사이드막 상에 마스크층을 형성하는 단계, 및 염소가스(Cl2)와 산소가스(O2)의 혼합가스를 사용하여 상기 실리사이드막 및 폴리실리콘막을 식각하는 단계를 포함하는 것을 특징으로 하는 폴리사이드 게이트 형성방법.
  2. 제1항에 있어서, 상기 산소가스(O2)는, 전체 식각가스 중의 10%∼30%의 비율로 첨가하는 것을 특징으로 하는 폴리사이드 게이트 형성방법.
  3. 제1항에 있어서, 상기 실리사이드막을 식각하는 단계는, 0℃이상의 온도에서 150W 이상의 바이어스 전력을 사용하여 진행되는 것을 특징으로 하는 폴리사이드 게이트 형성방법.
  4. 제1항에 있어서, 상기 실리사이드막을 식각하는 단계는, 0℃이하의 온도에서 200W 이상의 바이어스 전력을 사용하여 진행되는 것을 특징으로 하는 폴리사이드 게이트 형성방법.
  5. 반도체기판 상에 게이트절연막, 폴리실리콘막 및 실리사이드막을 차례로 형성하는 단계; 상기 실리사이드막 상에 마스크층을 형성하는 단계; 및 염소가스(Cl2), 산소가스(O2), 그리고 플로라인(F)을 함유하는 가스를 포함하는 식각가스를 사용하여 상기 실리사이드막 및 폴리실리콘막을 식각하는 단계를 포함하는 것을 특징으로 하는 폴리사이드 게이트 형성방법.
  6. 제5항에 있어서, 상기 마스크층은 실리콘질화막으로 형성하는 것을 특징으로 하는 폴리사이드 구조의 형성방법.
  7. 제6항에 있어서, 상기 마스크층은, 500℃이상의 온도에서 저압 화학기상 증착(LP-CVD) 방법으로 형성하는 것을 특징으로 하는 폴리사이드 게이트 형성방법.
  8. 제5항에 있어서, 상기 식각가스는, 염소가스(Cl2) 및 산소가스(O2)에 플로라인(F)을 포함하는 가스가 혼합된 가스인 것을 특징으로 하는 폴리사이드 게이트 형성방법.
  9. 제8항에 있어서, 상기 C-F계열의 가스는 총 유량의 80%이하를 사용하는 것을 특징으로 하는 폴리사이드 게이트 형성방법.
  10. 제5항에 있어서, 상기 식각가스는, 염소가스(Cl2), 산소가스(O2) 및 질소가스(N2)에 플로라인(F)을 포함하는 가스가 혼합된 가스인 것을 특징으로 하는 폴리사이드 게이트 형성방법.
  11. 제8항 내지 제10항 중의 어느 한 항에 있어서, 상기 플로라인(F)을 포함한 가스는, 육불화항(SF6) 및 사불화탄소(CF4)로 이루어진 그룹에서 선택된 어느 하나인 것을 특징으로 하는 폴리사이드 게이트 형성방법.
  12. 제8항 내지 제10항 중의 어느 한 항에 있어서, 상기 염소가스(Cl2)와 산소가스(O2)의 비는 4 : 1인 것을 특징으로 하는 폴리사이드 게이트 형성방법.
  13. 반도체기판 상에 게이트절연막, 폴리실리콘막 및 실리사이드막을 차례로 형성하는 단계; 상기 실리사이드막 상에 마스크층을 형성하는 단계; 및 염소가스(Cl2), 산소가스(O2), 그리고 탄소(C)-플로라인(F)계열의 가스를 포함하는 식각가스를 시용하여 상기 실리사이드막 및 폴리실리콘막을 식각하는 단계를 포함하는 것을 특징으로 하는 폴리사이드 게이트 형성방법.
  14. 제13항에 있어서, 상기 실리사이드막은, 화학기상증착(CVD) 방법으로 증착된 실리사이드막인 것을 특징으로 하는 폴리사이드 게이트 형성방법.
  15. 제13항에 있어서, 상기 C-F 계열의 가스는, 사불화탄소(CF4), 육불화에틸렌(C2F6), 십불화부탄(C4F10), 일불화메탄(CH3F)으로 이루어진 그룹에서 선택된 어느 하나를 사용하는 것을 특징으로 하는 폴리사이드 게이트 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970016816A 1996-05-15 1997-04-30 폴리사이드게이트형성방법 Expired - Fee Related KR100265756B1 (ko)

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US08/857,754 US6159811A (en) 1996-05-15 1997-05-15 Methods for patterning microelectronic structures using chlorine, oxygen, and fluorine

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KR016264 1996-05-15
KR19960016264 1996-05-15
KR1019960016264 1996-05-15

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CN1172343A (zh) 1998-02-04
CN1128466C (zh) 2003-11-19
US6087264A (en) 2000-07-11
JP4242463B2 (ja) 2009-03-25
JPH1055980A (ja) 1998-02-24
KR100265756B1 (ko) 2000-10-02

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