KR970077305A - 반도체 기판 에지의 손상 구역을 에칭하는 방법 및 에칭 장치 - Google Patents

반도체 기판 에지의 손상 구역을 에칭하는 방법 및 에칭 장치 Download PDF

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KR970077305A
KR970077305A KR1019970022988A KR19970022988A KR970077305A KR 970077305 A KR970077305 A KR 970077305A KR 1019970022988 A KR1019970022988 A KR 1019970022988A KR 19970022988 A KR19970022988 A KR 19970022988A KR 970077305 A KR970077305 A KR 970077305A
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semiconductor substrate
chamber
protective
etching
edge
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요제프 마투니
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로더리히 네테부쉬; 롤프 옴케
지멘스 악티엔게젤샤프트
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12Preparing bulk and homogeneous wafers
    • H10P90/128Preparing bulk and homogeneous wafers by edge treatment, e.g. chamfering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32357Generation remote from the workpiece, e.g. down-stream
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/32623Mechanical discharge control means
    • H01J37/32633Baffles
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/32715Workpiece holder
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/32798Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
    • H01J37/32807Construction (includes replacing parts of the apparatus)
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/32798Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
    • H01J37/32899Multiple chambers, e.g. cluster tools
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04Apparatus for manufacture or treatment
    • H10P72/0402Apparatus for fluid treatment
    • H10P72/0418Apparatus for fluid treatment for etching
    • H10P72/0421Apparatus for fluid treatment for etching for drying etching
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04Apparatus for manufacture or treatment
    • H10P72/0402Apparatus for fluid treatment
    • H10P72/0418Apparatus for fluid treatment for etching
    • H10P72/0422Apparatus for fluid treatment for etching for wet etching
    • H10P72/0424Apparatus for fluid treatment for etching for wet etching using mainly spraying means, e.g. nozzles
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16Coating processes; Apparatus therefor
    • G03F7/168Finishing the coated layer, e.g. drying, baking, soaking

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Weting (AREA)

Abstract

본 발명은 반도체 기판 전면(12)및 기판 후면(13)이 래커링되지 않은 상태에서 반도체 기판 에지(14)를 에칭할 수 있는 장치 및 방법을 제공한다. 본 발명에서 반도체 기판(11)에 진공화 가능한 프로세스 챔버(2)내에 배치된 보호 챔버(3)가 제공된다. 반도체 기판 전면(12) 및 기판 후면(13)은 에칭될 반도체 기판에지(14)에 이르기까지 상기 보호 챔버(3)에 의해 덮어진다. 반도체 기판 에지(14)위로 에칭제가 제공되고, 에칭 생성물 및 과량의 에칭제는 배출된다.

Description

반도체 기판 에지의 손상 구역을 에칭하는 방법 및 에칭 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 장치를 개략적으로 도시한 개략도이다.

Claims (14)

  1. a) 반도체 기판 전면(12) 및 기판 후면(13)을 에칭될 기판 에지(14)에 이르기까지 덮고 있는, 프로세스챔버(2)내에 배치된 보호 챔버(3)내에 반도체 기판(11)을 제공하는 단계, b) 반도체 기판의 에지(14) 위에 에칭제가 제공되고, 에칭 생성물 및 과량의 에칭제가 배출되는 단계에 의해, 반도체 기판 전면(12) 및 기판 후면(13)이 래커링되지 않은 상태에서 반도체 기판(11)의 에지(14)영역 위에 있는 손상 구역을 에칭하기 위한 방법.
  2. 제1항에 있어서, 반도체 기판 전면(12) 및 반도체 기판 에지(14) 영역 위에 보호 가스(16)가 리드되는 것을 특징으로 하는 방법.
  3. 제1항 또는 제2항에 있어서, 가스 또는 가스 혼합물을 에칭제(15)로서 사용하는 것을 특징으로 하는 방법.
  4. 제3항에 있어서, 가스 또는 가스 혼합물이 마이크로파 또는 고주파를 통해 플라즈마로 여기되고, 프로세스 챔버(2)는 진공화 되는 것을 특징으로 하는 방법.
  5. 제4항에 있어서, 플라즈마는 프로세스 챔버(2)에 의해 분리된 플라즈마 형성 챔버(25)내에서 형성되는 것을 특징으로 하는 방법.
  6. 제1항 또는 제2항에 있어서, 에칭제(15)로서 에칭 용액이 사용되고, 상기 에칭 용액을 반도체 기판 에지(14)위에 스프레이 하는 것을 특징으로 하는 방법.
  7. 제6항에 있어서, 반도체 기판(11) 및/또는 프로세스 챔버(2)를 ≤100℃의 온도로 가열하는 것을 특징으로 하는 방법.
  8. α) 프로세스 챔버(2), β) 제1보호 챔버(4)를 갖는 반도체 기판 전면(12) 및 제2보호 챔버(5)를 갖는 반도체 기판 후면(13)을 에칭될 반도체 기판 에지(14)까지 덮고 있는, 상기 프로세스 챔버(2)내에 배치된 보호챔버(3),및 에칭제(15)가 반도체 기판 에지(14) 위에 제공될 때 통과하는, 프로세스 챔버(2)에 배치된 에칭제 유입구(6)로 이루어진, 반도체 기판 전면(12) 및 기판 후면(13(이 래커링 되지 않은 상태로 반도체기판(11)의 에지(14) 영역 위에 있는 손상 구역을 에칭하기 위한 장치.
  9. 제8항에 있어서, 제1보호 챔버(4) 영역 및 제2보호 챔버(5) 영역에 각각 하나의 보호 가스 유입구(7)가 배치되고, 에칭 침식으로부터 반도체 기판 전면(12) 및 후면(13)을 보호하기 위해, 보호 가스(16)가 상기 유입구를 통해 래커링 되지 않은 반도체 기판 전면 및 기판 후면 위로 리드되는 것을 특징으로 하는 에칭 장치.
  10. 제9항에 있어서, 제1보호 챔버 영역(4)에는 하나의 헤드 플레이트(9)가 제공될 수 있고, 제2보호 챔버영역(5)에는 하단 플레이트(10)가 제공될 수 있으며, 상기 각 플레이트는 반도체 기판 전면(12) 및 기판 후면(13)의 중앙 영역에 배치된 적어도 하나의 개구(17)를 포함하고, 보호가스가 상기 개구를 통해 유입되는 것을 특징으로 하는 에칭 장치.
  11. 제10항에 있어서, 헤드 플레이트(9)및 하단 플레이트(10)의 외부 에지에 블라인드(18, 19)가 제공되고, 에칭될 반도체 기판 에지(14)를 제한하고 상기 블라인드(18, 19)를 감싸고 있는 외부 블라인드(20, 21)가 프로세스 챔버(2) 내부 쪼는 보호 챔버(4, 5)에 제공되며, 블라인드(18, 19)및 외부 블라인드(20, 21)사이에는 갭(22, 23)이 있어서, 리드된 보호 가스(16)가 상기 갭을 통해 배출되는 것을 특징으로 하는 에칭 장치.
  12. 제8항 내지 제11항 중 어느 한 항에 있어서, 제2보호 챔버 영역에 적어도 3개의 핀이 제공되고, 상기핀 위에 반도체 기판이 올려지는 것을 특징으로 하는 에칭 장치.
  13. 제8항 내지 제11항 중 어느 한 항에 있어서, 프로세스 챔버(2)내에 지지장치(24)가 제공되고, 반도체 기판(11)의 외부 에지(27)가 지지 장치 위에 정확하게 올려지는 것을 특징으로 하는 에칭 장치.
  14. 제8항 내지 제13항 중 어느 한 항에 있어서, 에칭 장치가 다중 챔버 장치의 구성 부품인 것을 특징으로 하는 에칭 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970022988A 1996-05-31 1997-05-31 반도체 기판 에지의 손상 구역을 에칭하는 방법 및 에칭 장치 Withdrawn KR970077305A (ko)

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DE19622015.7 1996-05-31
DE19622015A DE19622015A1 (de) 1996-05-31 1996-05-31 Verfahren zum Ätzen von Zerstörungszonen an einem Halbleitersubstratrand sowie Ätzanlage

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US (1) US5945351A (ko)
EP (1) EP0810641A3 (ko)
JP (1) JP2989565B2 (ko)
KR (1) KR970077305A (ko)
DE (1) DE19622015A1 (ko)
TW (1) TW358978B (ko)

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