KR970077505A - 평탄화된 필드 분리 영역 형성 방법 - Google Patents

평탄화된 필드 분리 영역 형성 방법 Download PDF

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KR970077505A
KR970077505A KR1019970018005A KR19970018005A KR970077505A KR 970077505 A KR970077505 A KR 970077505A KR 1019970018005 A KR1019970018005 A KR 1019970018005A KR 19970018005 A KR19970018005 A KR 19970018005A KR 970077505 A KR970077505 A KR 970077505A
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substrate
separation material
layer
material layer
forming
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KR1019970018005A
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KR100256830B1 (ko
Inventor
홍 셍 첸
취 시 텡
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클라크 3셈 존 엠
내셔널 세미컨덕터 코오포레이션
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

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  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

평탄화된 필드 분링 영역은 필드 분리 영역을 규정하도록 패턴된 기판에 산소 및 질소 이온과 같은 분리 재료를 주입함으로서 인접 반도체 장치와 분리하도록 반도체 기판에 형성된다. 기판의 표면으로부터 하부로 확장된 필드 분리 영역을 형성하기 위해 주입된 분리 재료를 기판의 실리콘과 결합시킨다.

Description

평탄화된 필드 분링 영역 형성 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4a도 내지 제4c도는 본 발명에 따른 평탄화된 필드 분리 영역을 형성하는 공정을 표시한 단면도.

Claims (6)

  1. 실리콘 기판의 필드 분리 영역을 형성하는 방법에 있어서, 상기 방법은, 기판상에 패턴 재료층을 형성하는 단계, 상기 기판의 표면 영역을 노출하기 위해 상기 패턴 재료층을 패터닝 및 에칭하는 단계, 상기 기판의 상면으로부터 하부로 확장하는 주입영역을 형성하기 위해 기판의 표면 영역에 분리 재료를 주입하는 단계, 및 상기 기판의 상면으로부터 하부로 확장하는 필드 분리 영역을 형성하기 위해 상기 주입 영역에 주입되 재료가 실리콘 기판과 결합하도록 기판을 어닐링하는 단계로 이루어지는 것을 특징으로 하는 방법.
  2. 제1항에 있어서, 상기 패턴 재료층이 산화물층 및 상부 실리콘 질화물층을 포함하는 것을 특징으로 하는 방법.
  3. 제1항에 있어서, 상기 분리 재료가 산소 이온을 포함하는 것을 특징으로 하는 방법.
  4. 제1항에 있어서, 상기 분리 재료가 질소 이온을 포함하는 것을 특징으로 하는 방법.
  5. 제1항에 있어서, 상기 주입단계가 우선하여 상기 기판 영역에 스크린 산화물층을 형성하는 단계를 더 구비하는 것을 특징으로 하는 방법.
  6. 제5항에 있어서, 상기 어닐링 단계에 우선하여 상기 분리 재료층을 제거하는 단계, 및 상기 어닐링 단계후에 상기 스크린 산화물층을 제거하는 단계를 더 구비하는 것을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970018005A 1996-05-09 1997-05-09 평탄화된 필드 분리 영역 형성 방법 Expired - Fee Related KR100256830B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US8/644,005 1996-05-09
US08/644,005 1996-05-09
US08/644,005 US5733813A (en) 1996-05-09 1996-05-09 Method for forming planarized field isolation regions

Publications (2)

Publication Number Publication Date
KR970077505A true KR970077505A (ko) 1997-12-12
KR100256830B1 KR100256830B1 (ko) 2000-05-15

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KR1019970018005A Expired - Fee Related KR100256830B1 (ko) 1996-05-09 1997-05-09 평탄화된 필드 분리 영역 형성 방법

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US (1) US5733813A (ko)
KR (1) KR100256830B1 (ko)
DE (1) DE19719272A1 (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6258693B1 (en) 1997-12-23 2001-07-10 Integrated Device Technology, Inc. Ion implantation for scalability of isolation in an integrated circuit
US6069054A (en) * 1997-12-23 2000-05-30 Integrated Device Technology, Inc. Method for forming isolation regions subsequent to gate formation and structure thereof
US6353246B1 (en) 1998-11-23 2002-03-05 International Business Machines Corporation Semiconductor device including dislocation in merged SOI/DRAM chips
US6245639B1 (en) 1999-02-08 2001-06-12 Taiwan Semiconductor Manufacturing Company Method to reduce a reverse narrow channel effect for MOSFET devices
US6232170B1 (en) * 1999-06-16 2001-05-15 International Business Machines Corporation Method of fabricating trench for SOI merged logic DRAM
US6432798B1 (en) * 2000-08-10 2002-08-13 Intel Corporation Extension of shallow trench isolation by ion implantation
EP1230677A1 (en) * 2000-08-21 2002-08-14 Koninklijke Philips Electronics N.V. Process for forming shallow isolating regions in an integrated circuit and an integrated circuit thus formed
US6486043B1 (en) 2000-08-31 2002-11-26 International Business Machines Corporation Method of forming dislocation filter in merged SOI and non-SOI chips
US7259053B2 (en) * 2003-09-22 2007-08-21 Dongbu Electronics Co., Ltd. Methods for forming a device isolation structure in a semiconductor device
KR100571412B1 (ko) * 2003-12-26 2006-04-14 동부아남반도체 주식회사 반도체 소자의 제조 방법
FR2876220B1 (fr) * 2004-10-06 2007-09-28 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.
FR2897982B1 (fr) 2006-02-27 2008-07-11 Tracit Technologies Sa Procede de fabrication des structures de type partiellement soi, comportant des zones reliant une couche superficielle et un substrat
US8399957B2 (en) 2011-04-08 2013-03-19 International Business Machines Corporation Dual-depth self-aligned isolation structure for a back gate electrode

Family Cites Families (8)

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US3897274A (en) * 1971-06-01 1975-07-29 Texas Instruments Inc Method of fabricating dielectrically isolated semiconductor structures
DE2941653A1 (de) * 1979-10-15 1981-04-23 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung von mos-transistoren
FR2616590B1 (fr) * 1987-06-15 1990-03-02 Commissariat Energie Atomique Procede de fabrication d'une couche d'isolant enterree dans un substrat semi-conducteur par implantation ionique et structure semi-conductrice comportant cette couche
JPH0210835A (ja) * 1988-06-29 1990-01-16 Nec Corp 半導体装置の製造方法
JPH0324727A (ja) * 1989-06-22 1991-02-01 Toshiba Corp 半導体装置の製造方法
JPH05121540A (ja) * 1991-10-24 1993-05-18 Mitsubishi Electric Corp 半導体装置の製造方法
US5393693A (en) * 1994-06-06 1995-02-28 United Microelectronics Corporation "Bird-beak-less" field isolation method
JPH0888232A (ja) * 1994-09-16 1996-04-02 Fuji Electric Co Ltd 縦型ｍｏｓ半導体素子の製造方法

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Publication number Publication date
KR100256830B1 (ko) 2000-05-15
DE19719272A1 (de) 1997-11-13
US5733813A (en) 1998-03-31

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