NL1027962A1 - Multi-chipverpakking, halfgeleiderinrichting daarin gebruikt en vervaardigingswijze daarvoor. - Google Patents

Multi-chipverpakking, halfgeleiderinrichting daarin gebruikt en vervaardigingswijze daarvoor.

Info

Publication number
NL1027962A1
NL1027962A1 NL1027962A NL1027962A NL1027962A1 NL 1027962 A1 NL1027962 A1 NL 1027962A1 NL 1027962 A NL1027962 A NL 1027962A NL 1027962 A NL1027962 A NL 1027962A NL 1027962 A1 NL1027962 A1 NL 1027962A1
Authority
NL
Netherlands
Prior art keywords
semiconductor device
device used
chip package
chip
manufacture therefor
Prior art date
Application number
NL1027962A
Other languages
English (en)
Other versions
NL1027962C2 (nl
Inventor
Heung-Kyu Kwon
Hee-Seok Lee
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020040040420A external-priority patent/KR100632476B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of NL1027962A1 publication Critical patent/NL1027962A1/nl
Application granted granted Critical
Publication of NL1027962C2 publication Critical patent/NL1027962C2/nl

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117Shapes of semiconductor bodies
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5445Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/547Dispositions of multiple bond wires
    • H10W72/5473Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/932Plan-view shape, i.e. in top view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • H10W90/24Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • H10W90/28Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • H10W90/291Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
NL1027962A 2004-01-13 2005-01-05 Multi-chipverpakking, halfgeleiderinrichting daarin gebruikt en vervaardigingswijze daarvoor. NL1027962C2 (nl)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20040002369 2004-01-13
KR20040002369 2004-01-13
KR1020040040420A KR100632476B1 (ko) 2004-01-13 2004-06-03 멀티칩 패키지 및 이에 사용되는 반도체칩
KR20040040420 2004-06-03

Publications (2)

Publication Number Publication Date
NL1027962A1 true NL1027962A1 (nl) 2005-07-14
NL1027962C2 NL1027962C2 (nl) 2006-02-20

Family

ID=36121603

Family Applications (1)

Application Number Title Priority Date Filing Date
NL1027962A NL1027962C2 (nl) 2004-01-13 2005-01-05 Multi-chipverpakking, halfgeleiderinrichting daarin gebruikt en vervaardigingswijze daarvoor.

Country Status (6)

Country Link
US (1) US7327020B2 (nl)
JP (1) JP4808408B2 (nl)
CN (1) CN1641873A (nl)
DE (1) DE102005002631B4 (nl)
NL (1) NL1027962C2 (nl)
TW (1) TWI278947B (nl)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297548B1 (en) 1998-06-30 2001-10-02 Micron Technology, Inc. Stackable ceramic FBGA for high thermal applications
US6351028B1 (en) * 1999-02-08 2002-02-26 Micron Technology, Inc. Multiple die stack apparatus employing T-shaped interposer elements
JP4553720B2 (ja) * 2004-12-21 2010-09-29 Okiセミコンダクタ株式会社 半導体装置及びその製造方法
JP2006210402A (ja) * 2005-01-25 2006-08-10 Matsushita Electric Ind Co Ltd 半導体装置
JP4408832B2 (ja) * 2005-05-20 2010-02-03 Necエレクトロニクス株式会社 半導体装置
KR100721353B1 (ko) * 2005-07-08 2007-05-25 삼성전자주식회사 칩 삽입형 매개기판의 구조와 제조 방법, 이를 이용한 이종칩의 웨이퍼 레벨 적층 구조 및 패키지 구조
JP4716836B2 (ja) * 2005-10-05 2011-07-06 パナソニック株式会社 半導体装置
KR100764682B1 (ko) * 2006-02-14 2007-10-08 인티그런트 테크놀로지즈(주) 집적회로 칩 및 패키지.
US7420206B2 (en) * 2006-07-12 2008-09-02 Genusion Inc. Interposer, semiconductor chip mounted sub-board, and semiconductor package
US20080029885A1 (en) * 2006-08-07 2008-02-07 Sandisk Il Ltd. Inverted Pyramid Multi-Die Package Reducing Wire Sweep And Weakening Torques
US20080032451A1 (en) * 2006-08-07 2008-02-07 Sandisk Il Ltd. Method of providing inverted pyramid multi-die package reducing wire sweep and weakening torques
JP2008103571A (ja) * 2006-10-19 2008-05-01 Toshiba Corp 半導体装置及びその製造方法
CN101279709B (zh) * 2007-04-04 2011-01-19 财团法人工业技术研究院 微型声波传感器的多层式封装结构
JP2009176978A (ja) * 2008-01-25 2009-08-06 Rohm Co Ltd 半導体装置
SG142321A1 (en) 2008-04-24 2009-11-26 Micron Technology Inc Pre-encapsulated cavity interposer
US8294251B2 (en) * 2008-06-30 2012-10-23 Sandisk Technologies Inc. Stacked semiconductor package with localized cavities for wire bonding
US8470640B2 (en) * 2008-06-30 2013-06-25 Sandisk Technologies Inc. Method of fabricating stacked semiconductor package with localized cavities for wire bonding
KR101118719B1 (ko) * 2008-06-30 2012-03-13 샌디스크 코포레이션 와이어 접합을 위한 국소 공동을 구비한 적층 반도체 패키지 및 그 제조 방법
KR20100046760A (ko) 2008-10-28 2010-05-07 삼성전자주식회사 반도체 패키지
JP2010199286A (ja) * 2009-02-25 2010-09-09 Elpida Memory Inc 半導体装置
US9466561B2 (en) 2009-08-06 2016-10-11 Rambus Inc. Packaged semiconductor device for high performance memory and logic
JP5646830B2 (ja) 2009-09-02 2014-12-24 ルネサスエレクトロニクス株式会社 半導体装置、半導体装置の製造方法、及びリードフレーム
US8018027B2 (en) * 2009-10-30 2011-09-13 Murata Manufacturing Co., Ltd. Flip-bonded dual-substrate inductor, flip-bonded dual-substrate inductor, and integrated passive device including a flip-bonded dual-substrate inductor
TWI501380B (zh) * 2010-01-29 2015-09-21 財團法人國家實驗研究院國家晶片系統設計中心 多基板晶片模組堆疊之三維系統晶片結構
US8598695B2 (en) * 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
KR20120062366A (ko) * 2010-12-06 2012-06-14 삼성전자주식회사 멀티칩 패키지의 제조 방법
CN103283023B (zh) * 2010-12-20 2016-09-14 英特尔公司 封装衬底中具有集成无源器件的集成数字和射频片上系统器件及其制造方法
US8637981B2 (en) 2011-03-30 2014-01-28 International Rectifier Corporation Dual compartment semiconductor package with temperature sensor
KR101222474B1 (ko) 2011-07-01 2013-01-15 (주)에프씨아이 반도체 패키지 및 그 반도체 패키지 제조방법
TWI473244B (zh) * 2011-10-05 2015-02-11 鉅景科技股份有限公司 堆疊式半導體封裝結構
CN104681510A (zh) * 2013-12-03 2015-06-03 晟碟信息科技(上海)有限公司 用于嵌入半导体裸片的桥结构
KR101849835B1 (ko) 2014-11-12 2018-04-17 인텔 코포레이션 웨어러블 디바이스용 가요성 시스템-인-패키지 솔루션
JP6523999B2 (ja) * 2016-03-14 2019-06-05 東芝メモリ株式会社 半導体装置およびその製造方法
JP6755842B2 (ja) * 2017-08-28 2020-09-16 株式会社東芝 半導体装置、半導体装置の製造方法及び半導体パッケージの製造方法
JP2019161007A (ja) * 2018-03-13 2019-09-19 株式会社東芝 半導体装置及びその製造方法
CN108766974A (zh) * 2018-08-08 2018-11-06 苏州晶方半导体科技股份有限公司 一种芯片封装结构以及芯片封装方法
DE102019126028A1 (de) * 2019-09-26 2021-04-01 Robert Bosch Gmbh Multichipanordnung und entsprechendes Herstellungsverfahren
CN110828442A (zh) * 2019-11-04 2020-02-21 弘凯光电(深圳)有限公司 封装结构及其制作方法
US12230598B2 (en) * 2021-02-22 2025-02-18 Mediatek Inc. Semiconductor package
KR20230008932A (ko) 2021-07-07 2023-01-17 삼성전자주식회사 반도체 패키지
US12564096B2 (en) * 2022-08-02 2026-02-24 Micron Technology, Inc. Nested semiconductor assemblies and methods for making the same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100393094B1 (ko) 1999-12-09 2003-07-31 앰코 테크놀로지 코리아 주식회사 지지각을 갖는 기판을 이용한 반도체 패키지
JP3888854B2 (ja) * 2001-02-16 2007-03-07 シャープ株式会社 半導体集積回路の製造方法
JP4633971B2 (ja) 2001-07-11 2011-02-16 ルネサスエレクトロニクス株式会社 半導体装置
KR20030018204A (ko) * 2001-08-27 2003-03-06 삼성전자주식회사 스페이서를 갖는 멀티 칩 패키지
DE10142119B4 (de) * 2001-08-30 2007-07-26 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zu seiner Herstellung
JP2003086734A (ja) * 2001-09-12 2003-03-20 Nec Corp Cspのチップスタック構造
US7332819B2 (en) * 2002-01-09 2008-02-19 Micron Technology, Inc. Stacked die in die BGA package
JP3507059B2 (ja) 2002-06-27 2004-03-15 沖電気工業株式会社 積層マルチチップパッケージ
DE10209204B4 (de) * 2002-03-04 2009-05-14 Infineon Technologies Ag Elektronisches Bauteil mit einem Stapel aus Halbleiterchips und Verfahren zur Herstellung desselben
JP2003282817A (ja) * 2002-03-27 2003-10-03 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US6737738B2 (en) * 2002-07-16 2004-05-18 Kingston Technology Corporation Multi-level package for a memory module
JP4052078B2 (ja) * 2002-10-04 2008-02-27 富士通株式会社 半導体装置

Also Published As

Publication number Publication date
DE102005002631A1 (de) 2005-08-11
TW200525671A (en) 2005-08-01
DE102005002631B4 (de) 2007-05-03
US7327020B2 (en) 2008-02-05
JP2005203776A (ja) 2005-07-28
CN1641873A (zh) 2005-07-20
JP4808408B2 (ja) 2011-11-02
US20050194673A1 (en) 2005-09-08
NL1027962C2 (nl) 2006-02-20
TWI278947B (en) 2007-04-11

Similar Documents

Publication Publication Date Title
NL1027962A1 (nl) Multi-chipverpakking, halfgeleiderinrichting daarin gebruikt en vervaardigingswijze daarvoor.
TW200707698A (en) Semiconductor device, manufacturing method for semiconductor device, and electronic equipment
TWI264756B (en) Semiconductor device
TW200608540A (en) Stacked packaging methods and structures
TW200511453A (en) Methods and apparatus for packaging integrated circuit devices
TW200634946A (en) Device and method for fabricating double-sided SOI wafer scale package with through via connections
TW200725709A (en) Semiconductor apparatus and making method thereof
SG149062A1 (en) Dicing die-bonding film
AU2003211575A1 (en) Semiconductor substrate, semiconductor chip, and semiconductor device manufacturing method
IL175341A0 (en) Process for packaging components, and packaged components
TW200707632A (en) Semiconductor device and forming method thereof
TW200737469A (en) Semiconductor device and manufacturing method thereof
TW200735421A (en) LED semiconductor body and use of an LED semiconductor body
FR2842943B1 (fr) Procede de fabrication de film polymere conducteur anisotrope sur tranche de semi-conducteur
TW200614420A (en) Semiconductor structure and semiconductor process
TW200717772A (en) Semiconductor device
TW200725859A (en) Structure and method for packaging a chip
TW200625561A (en) Semiconductor device
TW200711081A (en) A method of manufacturing a semiconductor packages and packages made
SG148973A1 (en) Semiconductor device package having pseudo chips
TW200520136A (en) Adhesive sheet for processing semiconductors and method for processing semiconductors
TW200735293A (en) Semiconductor device, substrate and manufacturing method thereof
TW200615107A (en) Release film for encapsulation of semiconductor chip
TW200501391A (en) Semiconductor device
MX2007003615A (es) Circuito integrado y metodo de fabricacion.

Legal Events

Date Code Title Description
AD1A A request for search or an international type search has been filed
RD2N Patents in respect of which a decision has been taken or a report has been made (novelty report)

Effective date: 20051010

PD2B A search report has been drawn up
MK Patent expired because of reaching the maximum lifetime of a patent

Effective date: 20250104