NO20003508L - Adressering av minnematrise - Google Patents

Adressering av minnematrise

Info

Publication number
NO20003508L
NO20003508L NO20003508A NO20003508A NO20003508L NO 20003508 L NO20003508 L NO 20003508L NO 20003508 A NO20003508 A NO 20003508A NO 20003508 A NO20003508 A NO 20003508A NO 20003508 L NO20003508 L NO 20003508L
Authority
NO
Norway
Prior art keywords
memory matrix
addressing memory
cells
array
matrix
Prior art date
Application number
NO20003508A
Other languages
English (en)
Other versions
NO20003508D0 (no
NO312699B1 (no
Inventor
Michael O Thompson
Per-Erik Nordal
Goeran Gustafsson
Johan Carlsson
Hans Gude Gudesen
Original Assignee
Thin Film Electronics Asa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thin Film Electronics Asa filed Critical Thin Film Electronics Asa
Priority to NO20003508A priority Critical patent/NO312699B1/no
Publication of NO20003508D0 publication Critical patent/NO20003508D0/no
Priority to EP01975041A priority patent/EP1299885B1/en
Priority to CNB018124666A priority patent/CN1265394C/zh
Priority to AU2001294410A priority patent/AU2001294410B2/en
Priority to DE60108636T priority patent/DE60108636T2/de
Priority to KR10-2003-7000191A priority patent/KR100484580B1/ko
Priority to AU9441001A priority patent/AU9441001A/xx
Priority to CA002412169A priority patent/CA2412169C/en
Priority to HK04100107.6A priority patent/HK1057287B/xx
Priority to AT01975041T priority patent/ATE288124T1/de
Priority to PCT/NO2001/000289 priority patent/WO2002005287A1/en
Priority to ES01975041T priority patent/ES2232666T3/es
Priority to JP2002508805A priority patent/JP4472921B2/ja
Priority to US09/899,093 priority patent/US6804138B2/en
Priority to RU2003103443/09A priority patent/RU2239889C1/ru
Priority to US09/899,096 priority patent/US20020024835A1/en
Publication of NO20003508L publication Critical patent/NO20003508L/no
Publication of NO312699B1 publication Critical patent/NO312699B1/no
Priority to US10/934,573 priority patent/US6950330B2/en
Priority to JP2006287634A priority patent/JP2007087579A/ja

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/06—Passive matrix structure, i.e. with direct application of both column and row voltages to the light emitting or modulating elements, other than LCD or OLED
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
NO20003508A 2000-07-07 2000-07-07 Adressering av minnematrise NO312699B1 (no)

Priority Applications (18)

Application Number Priority Date Filing Date Title
NO20003508A NO312699B1 (no) 2000-07-07 2000-07-07 Adressering av minnematrise
US09/899,096 US20020024835A1 (en) 2000-07-07 2001-07-06 Non-volatile passive matrix device and method for readout of the same
HK04100107.6A HK1057287B (en) 2000-07-07 2001-07-06 Method for addressing of memory matrix
PCT/NO2001/000289 WO2002005287A1 (en) 2000-07-07 2001-07-06 Addressing of memory matrix
AU2001294410A AU2001294410B2 (en) 2000-07-07 2001-07-06 Addressing of memory matrix
DE60108636T DE60108636T2 (de) 2000-07-07 2001-07-06 Adressierung einer speichermatrix
KR10-2003-7000191A KR100484580B1 (ko) 2000-07-07 2001-07-06 메모리 매트릭스의 어드레싱
AU9441001A AU9441001A (en) 2000-07-07 2001-07-06 Addressing of memory matrix
CA002412169A CA2412169C (en) 2000-07-07 2001-07-06 Addressing of memory matrix
EP01975041A EP1299885B1 (en) 2000-07-07 2001-07-06 Addressing of memory matrix
AT01975041T ATE288124T1 (de) 2000-07-07 2001-07-06 Adressierung einer speichermatrix
CNB018124666A CN1265394C (zh) 2000-07-07 2001-07-06 存储器矩阵的寻址方法
ES01975041T ES2232666T3 (es) 2000-07-07 2001-07-06 Direccionamiento de una matriz de memoria.
JP2002508805A JP4472921B2 (ja) 2000-07-07 2001-07-06 メモリマトリックスのアドレス指定
US09/899,093 US6804138B2 (en) 2000-07-07 2001-07-06 Addressing of memory matrix
RU2003103443/09A RU2239889C1 (ru) 2000-07-07 2001-07-06 Адресация матричной памяти
US10/934,573 US6950330B2 (en) 2000-07-07 2004-09-07 Addressing of memory matrix
JP2006287634A JP2007087579A (ja) 2000-07-07 2006-10-23 メモリマトリックスのアドレス指定

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NO20003508A NO312699B1 (no) 2000-07-07 2000-07-07 Adressering av minnematrise

Publications (3)

Publication Number Publication Date
NO20003508D0 NO20003508D0 (no) 2000-07-07
NO20003508L true NO20003508L (no) 2002-01-08
NO312699B1 NO312699B1 (no) 2002-06-17

Family

ID=19911359

Family Applications (1)

Application Number Title Priority Date Filing Date
NO20003508A NO312699B1 (no) 2000-07-07 2000-07-07 Adressering av minnematrise

Country Status (13)

Country Link
US (2) US6804138B2 (no)
EP (1) EP1299885B1 (no)
JP (2) JP4472921B2 (no)
KR (1) KR100484580B1 (no)
CN (1) CN1265394C (no)
AT (1) ATE288124T1 (no)
AU (2) AU9441001A (no)
CA (1) CA2412169C (no)
DE (1) DE60108636T2 (no)
ES (1) ES2232666T3 (no)
NO (1) NO312699B1 (no)
RU (1) RU2239889C1 (no)
WO (1) WO2002005287A1 (no)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6937500B2 (en) 2002-09-11 2005-08-30 Thin Film Electronics Asa Method for operating a ferroelectric of electret memory device, and a device of this kind

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US6756620B2 (en) * 2001-06-29 2004-06-29 Intel Corporation Low-voltage and interface damage-free polymer memory device
US6624457B2 (en) 2001-07-20 2003-09-23 Intel Corporation Stepped structure for a multi-rank, stacked polymer memory device and method of making same
NO314524B1 (no) * 2001-11-30 2003-03-31 Thin Film Electronics Asa Fremgangsmåte til lesing av celler i en passiv matriseadresserbar innretning, samt innretning for utförelse av fremgangsmåten
US6646904B2 (en) * 2001-12-21 2003-11-11 Intel Corporation Ferroelectric memory and method of reading the same
NO315399B1 (no) 2002-03-01 2003-08-25 Thin Film Electronics Asa Minnecelle
JP4214708B2 (ja) * 2002-03-27 2009-01-28 セイコーエプソン株式会社 強誘電体記憶装置及びその駆動方法
GB2390201A (en) * 2002-06-27 2003-12-31 Seiko Epson Corp Charge integrating sense amplifier
US6920060B2 (en) 2002-08-14 2005-07-19 Intel Corporation Memory device, circuits and methods for operating a memory device
JP2005032401A (ja) * 2003-06-17 2005-02-03 Sharp Corp 不揮発性半導体記憶装置及びその書き込み方法と消去方法
US7236394B2 (en) * 2003-06-18 2007-06-26 Macronix International Co., Ltd. Transistor-free random access memory
NO324607B1 (no) * 2003-11-24 2007-11-26 Thin Film Electronics Asa Fremgangsmate for a betjene et datalagringsapparat som benytter passiv matriseadressering
NO320149B1 (no) * 2004-02-13 2005-10-31 Thin Film Electronics Asa Fremgangsmate for a drive en ferroelektrisk eller elektret minneinnretning
US7133304B2 (en) * 2004-03-22 2006-11-07 Texas Instruments Incorporated Method and apparatus to reduce storage node disturbance in ferroelectric memory
NO322040B1 (no) 2004-04-15 2006-08-07 Thin Film Electronics Asa Bimodal drift av ferroelektriske og elektrete minneceller og innretninger
JP4753873B2 (ja) * 2004-06-23 2011-08-24 パトレネラ キャピタル リミテッド， エルエルシー メモリ
NO324029B1 (no) * 2004-09-23 2007-07-30 Thin Film Electronics Asa Lesemetode og deteksjonsanordning
JP2008527584A (ja) * 2005-01-04 2008-07-24 シン フイルム エレクトロニクス エイエスエイ 受動マトリクス・アドレッシング方式の強誘電体又はエレクトレット・メモリ・デバイスの動作方法
US7215565B2 (en) 2005-01-04 2007-05-08 Thin Film Electronics Asa Method for operating a passive matrix-addressable ferroelectric or electret memory device
US7706165B2 (en) * 2005-12-20 2010-04-27 Agfa-Gevaert Nv Ferroelectric passive memory cell, device and method of manufacture thereof
JP4718354B2 (ja) * 2006-03-27 2011-07-06 パトレネラ キャピタル リミテッド， エルエルシー メモリ
US20080037324A1 (en) * 2006-08-14 2008-02-14 Geoffrey Wen-Tai Shuy Electrical thin film memory
EP1944763A1 (en) 2007-01-12 2008-07-16 STMicroelectronics S.r.l. Reading circuit and method for data storage system
US7813158B2 (en) * 2007-05-14 2010-10-12 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Recordable electrical memory
US7679967B2 (en) * 2007-12-21 2010-03-16 Spansion Llc Controlling AC disturbance while programming
WO2009102918A1 (en) * 2008-02-13 2009-08-20 Hong Kong Applied Science & Technology Research Institute Co. Ltd Recordable memory cell with multiple physical states
US7791976B2 (en) 2008-04-24 2010-09-07 Qualcomm Incorporated Systems and methods for dynamic power savings in electronic memory operation
JP2008276935A (ja) * 2008-06-27 2008-11-13 Seiko Epson Corp 強誘電体記憶装置、その駆動方法及び駆動回路
JP2011022497A (ja) * 2009-07-17 2011-02-03 Seiko Epson Corp 電気光学装置、電子機器、及び電気光学装置の駆動方法
US9224465B2 (en) * 2014-03-21 2015-12-29 Intel Corporation Cross-point memory bias scheme
US9886571B2 (en) 2016-02-16 2018-02-06 Xerox Corporation Security enhancement of customer replaceable unit monitor (CRUM)
US9613676B1 (en) * 2016-06-29 2017-04-04 Micron Technology, Inc. Writing to cross-point non-volatile memory
US10978169B2 (en) 2017-03-17 2021-04-13 Xerox Corporation Pad detection through pattern analysis
US10529410B2 (en) 2017-12-18 2020-01-07 Micron Technology, Inc. Techniques for accessing an array of memory cells to reduce parasitic coupling
US10762944B2 (en) 2017-12-18 2020-09-01 Micron Technology, Inc. Single plate configuration and memory array operation
US10504576B2 (en) * 2017-12-19 2019-12-10 Micron Technology, Inc. Current separation for memory sensing
US10446232B2 (en) * 2017-12-19 2019-10-15 Micron Technology, Inc. Charge separation for memory sensing
US10497521B1 (en) 2018-10-29 2019-12-03 Xerox Corporation Roller electric contact
US11017831B2 (en) 2019-07-15 2021-05-25 Micron Technology, Inc. Ferroelectric memory cell access
US11348635B2 (en) 2020-03-30 2022-05-31 Micron Technology, Inc. Memory cell biasing techniques during a read operation
US20250322886A1 (en) * 2024-04-15 2025-10-16 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device and operating method thereof

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6937500B2 (en) 2002-09-11 2005-08-30 Thin Film Electronics Asa Method for operating a ferroelectric of electret memory device, and a device of this kind

Also Published As

Publication number Publication date
NO20003508D0 (no) 2000-07-07
US20020060923A1 (en) 2002-05-23
US6950330B2 (en) 2005-09-27
CA2412169C (en) 2005-12-27
HK1057287A1 (en) 2004-03-19
AU9441001A (en) 2002-01-21
CN1265394C (zh) 2006-07-19
WO2002005287A1 (en) 2002-01-17
RU2239889C1 (ru) 2004-11-10
CN1440553A (zh) 2003-09-03
AU2001294410B2 (en) 2006-01-05
JP2004503051A (ja) 2004-01-29
ATE288124T1 (de) 2005-02-15
EP1299885B1 (en) 2005-01-26
JP2007087579A (ja) 2007-04-05
KR20030041955A (ko) 2003-05-27
EP1299885A1 (en) 2003-04-09
CA2412169A1 (en) 2002-01-17
US20050058010A1 (en) 2005-03-17
ES2232666T3 (es) 2005-06-01
US6804138B2 (en) 2004-10-12
KR100484580B1 (ko) 2005-04-22
NO312699B1 (no) 2002-06-17
DE60108636D1 (de) 2005-03-03
JP4472921B2 (ja) 2010-06-02
DE60108636T2 (de) 2005-06-23

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