PL149596B2 - A system of a simple juvenile personal microcomputer - Google Patents

Description

Layout of a simple personal microcomputer for teenagers

The subject of the invention is a simple personal microcomputer system for teenagers.

The layout of a simple personal microcomputer is complicated in that its circuitry must incorporate not only its own microprocessor, but also circuitry for displaying graphic information in a reproducing unit (TV set or monitor). In principle, it is possible to solve the problem in three ways.

The first method consists in dividing the RAM memory in such a way that there is a separate RAM memory at the processor as well as at the reproducing part. The processor must then be able to access both RAMs and thus the circuits for addresses and data switching between the processor and the reproduction portion will be complex. For a simple computer, it is useful to save RAM, and therefore this solution is not preferable.

The second way is to use common RAM memory for the processor and for the reproduction part. In this case, the circuits for addresses and data switching between the processor and the reproducing part must be turned on again in the computer, and then the synchronization circuits for the processor to reach the RAM memory. For efficient cooperation of the reproducing part and the processor, it is necessary to have a fast RAM memory and a fast processor available, which places higher demands on the control logic, component tolerances and power consumption. Higher energy requirements also affect the cooling requirements of the computer.

The third type is the use of direct memory access. For this, however, it is necessary to use a DMA control system / e.g. the 8257 / type chip, which, however, does not have the speed sufficient for high-density graphical representation, since its maximum transfer rate is 500 kilobytes / sec. Possibly using a special circuit - a control system for graphic display - is uneconomical in a simple personal computer. Such a control system has either additional parameters / e.g. NEC 7220 / or they require the use of many additional circuits / e.g. MOTOROLA 6845 /. ’

The described disadvantages are remedied according to the invention by a simple personal computer for teenagers. The circuit consists of multiple input terminal, horizontal and vertical timing generator, ROM and RAM, shift register, block

149 596 of an OR combination element, a monostable circuit block, a TV signal generation block, a clock generator control block, an address decoder block, a control signal generator block, an oscillator, a frequency divider, a decoder, a DMA demand block, a microprocessor, and an output terminal. Its basic feature is that the multiple input terminal is connected to the second multiple input of the timing generator control block. The first multiple output of the timing generator control block is coupled to the second multiple input of the horizontal timing generator. The second multiple output of the timing generator control block is connected to the second multiple input of the vertical timing generator.

The first output of the horizontal timing generator is connected to the second input of the OR element block. The second output of the horizontal clock generator is connected to the second input of the monostable circuit block and also to the fourth input of the vertical clock generator. First, the output of the vertical clock generator is connected to the first input of the OR element block and also to the input of the DMA demand block. The second output of the vertical clock generator is connected to the first input of the monostable circuit block and also to the second input of the microprocessor. The output of the DMA demand block is connected to the fourth input of the microprocessor. The output of the OR element block is connected to the second input of the TV signal production block. The output of the monostable circuit block is connected to the first input of the TV signal generation block. The oscillator output is connected to the input of the frequency divider and also to the third shift register input.

The first output of the frequency divider is connected to the third input of the microprocessor. The second multiple output of the frequency divider is coupled to the first multiple input of the decoder. The third output of the frequency divider is connected to the second input of the control signal generator block. The fourth output of the frequency divider is linked to the fourth input of the horizontal clock. The first output of the decoder is coupled to the second input of the shift register. The second output of the decoder is connected to the third input of the horizontal clock generator and also to the third input of the vertical clock generator. The output of the shift register is connected to the third input of the control signal generation block. The microprocessor's first bi-directional multiple input is connected to the first bi-directional multiple ROM input and also to the first bi-directional multiple RAM input and the first multiple shift register input. The first multiple output of the microprocessor is connected to the first multiple input of the address decoder block and also to the third multiple ROM input, the third multiple RAM input, and the first bidirectional multiple input of the vertical clock generator.

The second multiple output of the microprocessor is connected to the second multiple input of the address decoder block and also to the second multiple input of ROM, the second multiple input of RAM and the first two-way multiple input of the horizontal clock generator. The third output of the microprocessor is connected to the first input of the timing generator control block and also to the third input of the address decoder block, the third input of the control signal generator block and the second input of the decoder. The fourth multiple output of the microprocessor is coupled to the first multiple input of the control signal generator block. The multiple output of the control signal generator block is coupled to a fifth multiple RAM input. The first output of the address decoder is coupled to the fourth input of a ROM. The second output of the address decoder block is coupled to the fourth RAM input. The output of the control signal generation block is connected to the output terminal.

The simple youth personal computer system of the present invention serves to implement the time base in displaying the system according to the Czechoslovak invention AO / PV 53-86 / "Television warp display time base system." This time base does not require an additional circuit for address switching between the processor and the pointer device. Next, a direct memory access / DMA move / is used for the indications. In this system, admittedly, the speed of the microprocessor remains

149 596 used in 25%, but the system is simple and the speed of the microcomputer is sufficient for school learning and the implementation of own applications. The entire system does not require a special circuit and the total number of circuits is minimal. The system does not impose high requirements as to the speed of construction elements, so the microcomputer has large time reserves, which has a positive effect on its reliability and reduces the power consumption of the entire microcomputer. Moreover, here the circuit is provided with programmability of the timing parameters of the sync and blanking pulses so that it is possible to maximize the speed of the processor by programming the display with a limited number of lines. The number of indicated lines, the number of points on one line, and the position of the image on the screen of the reproduction unit can be selected as desired when programming the time base function, and all these parameters can be changed dynamically by the program. It is also not necessary to use two RAMs in the system, which is advantageous when using a new dynamic memory, e.g. 64 kilobits.

All the simplicity of the circuit has been achieved by directly connecting the second multiple address output of the microprocessor to the first two-way multiple data input of the horizontal timing generator, with the second multiple address input of ROM and a second multiple address input of RAM, as well as by directly connecting the first multiple address output of the microcomputer with a first bidirectional multiple input of the vertical clock generator, with a third multiple address input of a ROM, and with a third multiple address input of a RAM memory. By this direct connection - while maintaining the possibility of programming both clock generators with addresses instead of with normal data - an extraordinary simplicity is achieved, not only regarding the number of components, but also the simplicity of the pattern of the printed circuit. With the arrangement of both timing generators according to the Czechoslovak invention AO / PV 53-86 /, the complex function of the time base and the DMA control circuit is achieved, thereby saving about twenty integrated circuits. This whole circuit is simpler from the point of view of simplicity than using modern, special VLSI type circuits. The 8253 type chip used is very cheap and available on an ongoing basis. When used as counters with outputs, they may then be used for addressing or pointing, moreover, they may be generally used for other purposes not only for addressing RAM data in graphical representation of the information on a personal computer.

A specific example of a simple youth personal microcomputer circuit according to this invention for an ONDRA small personal microcomputer is shown in the accompanying block diagram of the circuit.

The circuit consists of multiple input terminal 1, timing generator horizontal 2, vertical 3, ROM 4, RAM 5, shift register 6, OR block 7, monostable circuit block 8, TV signal generation block 9, control block 10 clock generator, address decoder block 11, control signal generator block 12, oscillator 13, frequency divider 14, decoder 15, DMA demand block 16, microprocessor 17, and output terminal 18.

Multiple input terminal 1 is connected to a second multiple input 194 of timer control block 10. The first multiple output 101 of the timing generator control block 10 is connected to the second multiple input 24 of the horizontal timing generator 2. The second multiple output 102 of the timing generator control 10 is connected to the second multiple input 34 of the vertical timing generator 3. The first output 22 of the horizontal timing generator 2 is connected to the second input 72 of block 7 of the OR element. The second output 23 of the horizontal timing generator 2 is connected to the second input 82 of the monostable system and also to the fourth input 36 of the vertical timing generator 3. The first output 32 of the vertical timing generator 3 is connected to the first input 71 of block 7 of the OR element and also to the input 161 of block 16. DMA demand. The second output 33 of the vertical clock generator 3 is connected to the first input 81 of the monostable block 8 and also to the second input 174 of the microprocessor 17. The output 162 of the DMA demand block 16 is connected to the fourth input 178 of the microprocessor 17. The output 73 of the Moku 7 of the OR element is connected to second input 93 of signal generation block 9

149 596 television. The output 131 of the oscillator 13 is connected to the input 141 of the frequency divider 14 and also to the third input 64 of the shift register 6. The first output 142 of the frequency divider 14 is connected to the third input 177 of the microprocessor 17. The second multiple output 143 of the frequency divider 14 is connected to the first multiple input. 151 of the decoder 15. The third output 144 of the frequency divider 14 is connected to the second input 123 of block 12 of the control signal generator. The fourth output 145 of the frequency divider 14 is connected to the fourth input 26 of the horizontal clock generator 2. The first output 152 of the decoder 15 is connected to the second input 63 of the shift register 6. The second output 153 of the decoder 15 is connected to the third input 25 of the horizontal clock generator 2 and also to the third input 35 of the vertical timing generator 3.

The output 62 of shift register 6 is connected to the third input 94 of TV signal generating block 9. The first bi-directional multiple input 171 of the microprocessor 17 is connected to the first bi-directional multiple input 41 of the ROM 4 and also to the first bi-directional multiple input 51 of the RAM 5 and also the first multiple input 61 of the shift register 6. The first multiple output 172 of the microprocessor 17 is connected with a first multiple input 111 of address decoder block 11 and also a third multiple input 43 of ROM 4, with a third multiple RAM input 53 and with a first bidirectional multiple input 31 of vertical clock generator 3. The second multiple output 173 of microprocessor 17 is connected to the second multiple input 112 of address decoder block 11 and also a second multiple input 42 of ROM 4, a second multiple input 52 of RAM 5 and a first bi-directional input 21 of horizontal timing generator 2.

The third output 175 of the microprocessor 17 is connected to the first input 193 of the clock control block 10 and also to the third input 113 of the address decoder block 11, to the third input 124 of the control signal generator block 12 and to the second input 154 of the decoder 15. The fourth multiple output 175 of the microprocessor 17 is connected to with the first multiple input 121 of block 12 of the control signal generator. The multiple output 122 of control signal generator 12 is coupled to the fifth multiple input 55 of the RAM 5. The first output 114 of the address decoder block 11 is coupled to the fourth input 44 of the ROM 4. The second output 115 of the address decoder block 11 is coupled to the fourth input. 54 of the RAM 5. An output 91 of the television signal generating block 9 is connected to an output terminal.

The basis of the circuit of a simple personal microcomputer for teenagers is the microprocessor 17, it is not important what type it is. The microprocessor 17 used only needs to be able based on the demand to perform collective data and address conduction for data transfer from RAM 5.

The fundamental frequency for the functional control of the microcomputer is produced in the oscillator 13. The output 131 of the oscillator 13 is fed to the third input 64 of the shift register 6 and through this connection the pulse frequency of the shift register 6 is transferred. From the output 131 of the oscillator 13, the frequency is fed to the input 141 of the frequency divider. 14. The frequency divider 14 divides, for example, by the number N = 8. The second multiple output 143 of the frequency divider 14 is fed to the first multiple input 151 of the decoder 15.

The decoder 15 decodes two of the eight states of the frequency divider 14. The first output 152 of the decoder 15 is at the active state of the second input 154 of the decoder 15 / DMA acknowledgment of the microprocessor 17 / signal T7, which is fed to the second input 63 of the shift register 6. This signal is displayed on the display. image controls the filling of data. On the second output 153 of the decoder 15 is at the active state of the second input 154 of the decoder 15 / DMA acknowledgment from the microprocessor 17 / signal TO, which controls reading memory data from the horizontal timing generator 2 using the third input 25 RD of the horizontal timing generator 2 and reading the memory addresses from vertical timing generator 3 via third input 35 RD of vertical timing generator 3. The first and second outputs 152, 153 of decoder 15 are only active in the picture display; the same occurs when the third output 175 of microprocessor 17 is active.

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The first output 142 of frequency divider 14 is fed to the third input 177 of microprocessor 17. From the fourth output 145 of frequency divider 14, a pulse of a given frequency is output to the fourth input 26 of horizontal clock generator 2. This frequency is 1 MHz and the transfer rate between RAM 5 and shift register 6 in image reproduction is 1 megabyte / sec. The third output 144 of the frequency divider 14 leads to the second input 123 of block 12 of the control signal generator. In block 12 of the control signal generator, it is created from the signal supplied to its second input 123 with the active state of the third input 124 of the control signal generator block 12 / DMA acknowledgment from the microprocessor 17 / request to read data from the RAM memory 5 and it is fed from multiple output 122 of the block 12 of the fifth multiple input 55 control signal generator 55 of the RAM memory 5.

Control signal generator block 12 continues to run even when the pictorial representation does not take place, i.e. when there are no DMA acknowledgments from microprocessor 17. Then the third input 124 of control signal generator 12 is inactive and microprocessor 17 gives control signals 176 on the fourth multiple output 176. for reading, renewing and writing to RAM 5, and block 12 of the control signal generator converts them on the first multiple input 121 of block 12 of control signal generator into control signals and forwards them via multiple output 122 of block 12 of control signal generator to the fifth multiple input 55 of the memory RAM type 5.

Microprocessor 17 supplies control signals to the fourth multiple output 176 of microprocessor 17. While not all control signals for describing the functions of a simple youth microcomputer circuit are of direct relevance, not all will be described in detail. Input, keyboard, printer and tape recorder attachment and other generally known parts will also not be discussed /. The microprocessor 17 supplies on the first multiple output 172 A1 of microprocessor 17 the lower half of the address / Al = 8 lower bits / and on the second multiple output 173 Ah the upper half of the address / Ah = 8 high bits /. Addresses will be routed to the second and third multiple inputs 42,43 of ROM 4 and to the second and third multiple inputs 52, 53 of RAM 5. The first bi-directional multiple input 171 of the microprocessor 17 is a data input and is bi-directional; when read, it transfers data to microprocessor 17 from ROM 4 through first bi-directional multiple input 41 of ROM 4 and from RAM 5 through first bi-directional multiple input of RAM 5, when input it transfers data from microprocessor 17 to RAM 5 through the first bidirectional multiple input 51 of RAM 5.

The first bi-directional multiple input 171, the first multiple output 172, the second multiple output 173, and the fourth multiple output 176 of the microprocessor 17 are only active while the microprocessor 17 is operating. Via the fourth input 178 of microprocessor 17, the environment of microprocessor 17 may need to transmit the control signal of microprocessor 17 from the second multiple output 173 Ah, the first multiple output 172 A1, the first bi-directional multiple input 171 DATA, and the fourth multiple output 176. Giving the response, microprocessor 17 switches to based on its fourth input 178, the demand of the second multiple output 173, the first multiple output 172, the first bi-directional multiple input 171, and the fourth multiple output 176 of the microprocessor 17 are fed into a so-called third state. Thereafter, an acknowledgment is issued on the third output 175 of microprocessor 17 about the sending of a so-called DMA acknowledgment. Demand and origin are generated by DMA requirement generating block 16.

Input 161 of DMA demand generation block 16 is fed to first output 32 of vertical clock generator 3. This signal is the actual vertical blanking pulse. If it were to be represented in the pictorial display unit, then input 161 of DMA generating block 16 becomes active and DMA generating block 16 generates a transmission of the demand on output 162 of DMA generating block 16, which is then applied to the fourth input 178 m and 6.

149 596 of the microprocessor 17. The microprocessor 17 confirms the transmission by activating the third output 175 Ak of the microprocessor 17. The third output 175 of the microprocessor 17 opens the function of the decoder 15 using the second input 154 of the decoder 15 and then switches the function of block 12 of the control signal generator using the third input 124 of block 12 control signal generator. The response of block 12 of the control signal generator and decoder 15 has already been described previously.

The third output 175 of microprocessor 17 is also coupled in block 11 of the address decoder to the third input 113 of block 11 of the address decoder. Address decoder block 11 decodes the top addresses of microprocessor 17 that go to the second multiple input 112 of the address decoder block 11 and the bottom addresses of microprocessor 17 that go to the first multiple input 111 of block 11 of the address decoder / normally it is sufficient to decode only one part of the high address bits of the top address /. When the third input 113 of address decoder block 11 is inactive, address decoder block 11 selects either ROM 4 by energizing the first output 114 of address decoder block 11 to be fed to the fourth input 44 of ROM 4 or RAM 5 by wake up the second output 115 of the address decoder block 11, which is fed to the fourth input 54 of the RAM 5. In the DMA acknowledgment, the third input 113 of the address decoder block 11 is active, and the address decoder block 11 operates such that regardless of the state of the first and of the second multiple input 111, 112 of the address decoder block 11 selects only the predetermined portion of RAM 5, namely by energizing the second output 115 of the address decoder block 11 to be fed to the fifth input 54 of the RAM 5. As a result, there is data that the imaging memory is part of the RAM 5, which is also selected for imaging and u regardless of the states of the second multiple output 173 and the first multiple output 172 of the microprocessor 17.

Block 1Θ of clock control is started by means of multiple input 104 of block 10 from multiple input terminal 1 by signals coming from inputs / figure no. Not selected - common part of each microcomputer /. Timing generator control block 10 provides for programming the vertical timing generator 3 by a program when the microcomputer is turned on or when imaging parameters / timing and blanking times are changed / The programming of both timing generators 2,3 is as follows: the first bidirectional multiple input 21 of the horizontal timing generator 2 is connected to the second multiple output 173 Ah of microprocessor 17, the first bi-directional multiple input 31 of vertical timing generator 3 is connected to first multiple output 172 A1 of microprocessor 17. The second multiple control input 24 of horizontal timing generator 2 is energized by the first multiple output 101 of generator control block 10 treating; the second multiple control input 24 of the vertical timing generator 3 is energized by the second multiple output 102 of the timing generator control block 10. Therefore, it is necessary to program the horizontal 2 and vertical 3 timing generator via the addresses of microprocessor 17, which is possible in conjunction with the timing generator control block 10. After programming, both clock generators 2 and 3 pass completely to their function. The horizontal timing generator 2 gives a horizontal timing on the second output 23 of the horizontal timing generator 2, which is applied to the second input 82 of block 8 of the monostable circuit and also to the fourth input 36 of the vertical timing generator, where it serves as the generator of the vertical part of the time base.

The first output 22 of horizontal timing generator 2 provides a horizontal blanking pulse that is applied to the second input 72 of block 7 of the OR element. The second output 33 of the vertical clock generator 3 is fed to the first input 81 of block 8 of the monostable circuit and also to the second input 174 of the microprocessor 17, where it has an interrupt requirement significance. The first output 32 of vertical timing generator 3 provides a field blanking pulse that is applied to the first input 71 of block 7 of the OR element. As also mentioned, this pulse also starts input 161 of the DMA demand generating block 16.

The monostable circuit block 8 converts the sync pulses of the first and second inputs 81, 82 of the monostable block into pulses of the required width and counts them together.

149 596

The timed timing pulses from the output 83 of the monostable circuit block 8 are fed as a timing signal to the first input 92 of TV-generating block 9.

The OR block 7 counts together the blanking pulses output from the horizontal 2 and vertical timing generator 3. The output 73 of the OR block 7 represents a video blanking signal that is fed to the second input 93 of TV generating block 9. The output 62 of shift register 6 leads to the third input 94 of TV signal generating block 9. Shift register 6 in imaging / third output 175 of microprocessor 17 is active / loaded with data going to multiple input 61 of shift register 6. Data comes from the first bidirectional multiple inputs 51 of RAM 5 which are addressed by the first bi-directional multiple input 21 of the horizontal clock generator 2 and by the first bi-directional multiple input 31 of the vertical timing generator 3. In shift register 6, the data is converted to a string and at the output 62 of the register shift 6, there is a video signal to control the light intensity of the imaging unit.

TV signal generation block 9 from synchronization pulses a TV signal displayed on a screen or on a television receiver on the first input 92 of the TV signal generating block 9 and a video signal on the third input 94 of the TV signal generating block 9 at the output 91 of the TV signal generating block 9, which is connected to output terminal 18.

Claims (1)

Simple youth microcomputer chip, including multiple input terminal, horizontal and vertical timing generator, ROM, RAM, shift register, LUB element block, monostable chip block, TV signal generation block, clock control block, address decoder block, control signal generator block, oscillator, frequency divider, decoder, DMA demand block, microprocessor and output terminal, characterized in that the multiple input terminal (1) is connected to the second multiple input (194) of the clock generator control block (18), the first multiple the output (101) of the timing generator control block (10) is connected to the second multiple input (24) of the horizontal timing generator (2), the second multiple output (102) of the timing generator control block (10) is connected to the second multiple input (34) of the timing generator (34) of the vertical clock (3), the first output (22) of the clock generator o the horizontal (2) is connected to the second input (72) of the OR block (7), the second output (23) of the horizontal timing generator (2) is connected to the second input (82) of the monostable block (8) and also to the fourth input (36) of the vertical clocking generator (3), the first output (32) of the clocking generator (3) is connected to the first input (71) of the OR block (7) and also to the input (161) of the DMA demand block (16), the second output (33) of the vertical clock generator (3) is connected to the first input (81) of the monostable circuit block (8) and also to the second input (174) of the microprocessor (17), the output (162) of the DMA demand block (16) is connected to the fourth input (178) of the microprocessor (17), the output (73) of the block (7) of the OR element is connected to the second input (93) of the TV signal generating block (9), the output (83) of the monostable circuit block (8) is connected to the first input (92) of a television signal production block (9), output (131) of the oscillator (13) is connected to the input (141) of the frequency divider (14) and also to the third input (64) of the shift register (6), the first output (142) of the frequency divider (14) is connected to the third input (177) ) of the microprocessor (17), the second multiple output (143) of the frequency divider (14) is connected to the first multiple input (151) of the decoder (15), the third output (144) of the frequency divider (14) is connected to the second input (123) of the block (12) of the control signal generator, the fourth output (145) of the frequency divider (14) is connected to the fourth input (26) of the horizontal timing generator (2), the first output (152) of the decoder (15) is connected to the second input (63) of the register 149 596 of shift (6), the second output (153) of the decoder (15) is connected to the third input (25) of the horizontal timing generator (2) and also to the third input (35) of the vertical timing generator (3), the register output (62) of the shift module (6) is coupled to the third input (94) of the television signal generating block (9), the first bi-directional multiple input (171) of the microprocessor (17) is coupled to the first bi-directional multiple input (41) of the ROM (4) and also to the with the first bi-directional multiple input (51) of RAM (5) and with the first multiple input (61) of shift register (6), the first multiple output (172) of the microprocessor (7) is connected to the first multiple input (111) of the decoder block (1) address and also a third multiple ROM input (43) (4), a third multiple RAM input (53) (5) and a vertical clock first bidirectional multiple input (31) (3), the second the multiple output (173) of the microprocessor (17) is connected to the second multiple input (172) of the address decoder block (11) and also to the second multiple input (42) of the ROM (4) with a second multiple input (52) of RAM (5) and with the first bidirectional input (21) of the horizontal timing generator (2), the third output (175) of the microprocessor (17) is connected to the first input (103) of the control block (10) and also to the third input (113) of the block (11) ) of the address decoder, with the third input (124) of the control signal generator block (12) and the second input (154) of the decoder, the fourth multiple output (176) of the microprocessor (17) is connected to the first multiple input (121) of the signal generator block (12) control signal generator, the multiple output (122) of the control signal generator (12) is coupled to the fifth multiple input (55) of the RAM (5), the first output (114) of the address decoder block (11) is coupled to the fourth input (44) p When the ROM voltage (4), the second output (115) of the decoder block (11) is connected to the fourth input (54) of the RAM (5) and the output (91) of the TV signal generating block (9) is connected to the output terminal (18). ).