SE453786B - Buffertkrets - Google Patents

Buffertkrets

Info

Publication number: SE453786B
Authority: SE; Sweden
Prior art keywords: signal; buffer; low; transition; delay
Prior art date: 1983-06-02

Application number

SE8402897A

Other languages

English (en)

Swedish (sv)

Other versions

SE8402897D0 (sv

SE8402897L (sv

Inventor

S P Saneski

Original Assignee

American Telephone & Telegraph

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1983-06-02

Filing date

1984-05-29

Publication date

1988-02-29

1984-05-29 Application filed by American Telephone & Telegraph filed Critical American Telephone & Telegraph

1984-05-29 Publication of SE8402897D0 publication Critical patent/SE8402897D0/xx

1984-12-03 Publication of SE8402897L publication Critical patent/SE8402897L/

1988-02-29 Publication of SE453786B publication Critical patent/SE453786B/sv

Links

239000000872 buffer Substances 0.000 title claims description 128
230000007704 transition Effects 0.000 claims description 61
230000003111 delayed effect Effects 0.000 description 21
230000001934 delay Effects 0.000 description 19
230000001850 reproductive effect Effects 0.000 description 6
230000004044 response Effects 0.000 description 4
230000000694 effects Effects 0.000 description 2
239000004020 conductor Substances 0.000 description 1
230000006870 function Effects 0.000 description 1
239000012146 running buffer Substances 0.000 description 1

Classifications

- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017545—Coupling arrangements; Impedance matching circuits

Landscapes

Engineering & Computer Science (AREA)
Computer Hardware Design (AREA)
Physics & Mathematics (AREA)
Computing Systems (AREA)
General Engineering & Computer Science (AREA)
Mathematical Physics (AREA)
Logic Circuits (AREA)
Dc Digital Transmission (AREA)
Amplifiers (AREA)
Manipulation Of Pulses (AREA)
Semiconductor Integrated Circuits (AREA)
Analogue/Digital Conversion (AREA)

SE8402897A 1983-06-02 1984-05-29 Buffertkrets SE453786B (sv)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
US06/500,419 US4575646A (en)	1983-06-02	1983-06-02	High-speed buffer arrangement with no delay distortion

Publications (3)

Publication Number	Publication Date
SE8402897D0 SE8402897D0 (sv)	1984-05-29
SE8402897L SE8402897L (sv)	1984-12-03
SE453786B true SE453786B (sv)	1988-02-29

Family

ID=23989338

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
SE8402897A SE453786B (sv)	1983-06-02	1984-05-29	Buffertkrets

Country Status (9)

Country	Link
US (1)	US4575646A (it)
JP (1)	JPS605627A (it)
CA (1)	CA1215137A (it)
DE (1)	DE3420239A1 (it)
FR (1)	FR2547135B1 (it)
GB (1)	GB2141600B (it)
IT (1)	IT1176241B (it)
NL (1)	NL8401768A (it)
SE (1)	SE453786B (it)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4782253A (en) *	1984-02-15	1988-11-01	American Telephone & Telegraph Company, At&T Bell Laboratories	High speed MOS circuits
US4786824A (en) *	1984-05-24	1988-11-22	Kabushiki Kaisha Toshiba	Input signal level detecting circuit
JPS61218143A (ja) *	1985-03-25	1986-09-27	Hitachi Ltd	半導体集積回路装置
JPS6235716A (ja) *	1985-08-09	1987-02-16	Hitachi Ltd	半導体集積回路装置
KR900001817B1 (ko) *	1987-08-01	1990-03-24	삼성전자 주식회사	저항 수단을 이용한 씨 모스 티티엘 인푸트 버퍼
CA1331214C (en) *	1989-01-05	1994-08-02	Kun-Ming Lee	Interfacing control circuit with active circuit charge or discharge
US4940908A (en) *	1989-04-27	1990-07-10	Advanced Micro Devices, Inc.	Method and apparatus for reducing critical speed path delays
FR2791370B1 (fr)	1999-03-22	2001-05-25	Sogreah	Bloc de carapace a surface rugueuse
NL2003428C2 (nl) *	2009-09-02	2011-03-03	Cremer Speciaalmachines B V	Vulinrichting.

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
GB1451732A (en) *	1973-03-19	1976-10-06	Motorola Inc	Signal shaping circuit
US3925689A (en) *	1974-09-13	1975-12-09	Gen Instrument Corp	High speed data buffer and amplifier
JPS5516539A (en) *	1978-07-20	1980-02-05	Nec Corp	Level shifter circuit
JPS5522238A (en) *	1978-07-31	1980-02-16	Fujitsu Ltd	Decoder circuit
US4318015A (en) *	1979-06-29	1982-03-02	Rca Corporation	Level shift circuit
US4314166A (en) *	1980-02-22	1982-02-02	Rca Corporation	Fast level shift circuits
EP0053214B1 (fr) *	1980-11-28	1987-08-26	International Business Machines Corporation	Système de distribution de signaux numériques
JPS58184817A (ja) *	1982-02-26	1983-10-28	Yokogawa Hewlett Packard Ltd	遅延回路

1983
- 1983-06-02 US US06/500,419 patent/US4575646A/en not_active Expired - Fee Related
1984
- 1984-05-23 CA CA000454939A patent/CA1215137A/en not_active Expired
- 1984-05-28 FR FR8408331A patent/FR2547135B1/fr not_active Expired
- 1984-05-29 SE SE8402897A patent/SE453786B/sv not_active IP Right Cessation
- 1984-05-30 DE DE19843420239 patent/DE3420239A1/de active Granted
- 1984-05-30 GB GB08413786A patent/GB2141600B/en not_active Expired
- 1984-06-01 NL NL8401768A patent/NL8401768A/nl not_active Application Discontinuation
- 1984-06-01 IT IT21227/84A patent/IT1176241B/it active
- 1984-06-02 JP JP59112226A patent/JPS605627A/ja active Pending

Also Published As

Publication number	Publication date
FR2547135A1 (fr)	1984-12-07
IT8421227A1 (it)	1985-12-01
SE8402897D0 (sv)	1984-05-29
IT1176241B (it)	1987-08-18
GB2141600B (en)	1986-09-17
IT8421227A0 (it)	1984-06-01
NL8401768A (nl)	1985-01-02
DE3420239C2 (it)	1992-12-10
CA1215137A (en)	1986-12-09
DE3420239A1 (de)	1984-12-06
JPS605627A (ja)	1985-01-12
GB2141600A (en)	1984-12-19
US4575646A (en)	1986-03-11
FR2547135B1 (fr)	1988-02-05
GB8413786D0 (en)	1984-07-04
SE8402897L (sv)	1984-12-03

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1995-01-31

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