SE7612468L - Sett att tillverka transistorer - Google Patents

Sett att tillverka transistorer

Info

Publication number
SE7612468L
SE7612468L SE7612468A SE7612468A SE7612468L SE 7612468 L SE7612468 L SE 7612468L SE 7612468 A SE7612468 A SE 7612468A SE 7612468 A SE7612468 A SE 7612468A SE 7612468 L SE7612468 L SE 7612468L
Authority
SE
Sweden
Prior art keywords
effect transistors
fabrication
way
submicron
gate field
Prior art date
Application number
SE7612468A
Other languages
English (en)
Other versions
SE428614B (sv
Inventor
Yau L Dy
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co filed Critical Western Electric Co
Publication of SE7612468L publication Critical patent/SE7612468L/sv
Publication of SE428614B publication Critical patent/SE428614B/sv

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
    • H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist

Landscapes

  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Bipolar Integrated Circuits (AREA)
SE7612468A 1975-11-20 1976-11-09 Sett att tillverka en halvledaranordning bl a innefattande trimning av ett resistmonster SE428614B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/633,602 US3997367A (en) 1975-11-20 1975-11-20 Method for making transistors

Publications (2)

Publication Number Publication Date
SE7612468L true SE7612468L (sv) 1977-05-21
SE428614B SE428614B (sv) 1983-07-11

Family

ID=24540323

Family Applications (1)

Application Number Title Priority Date Filing Date
SE7612468A SE428614B (sv) 1975-11-20 1976-11-09 Sett att tillverka en halvledaranordning bl a innefattande trimning av ett resistmonster

Country Status (11)

Country Link
US (1) US3997367A (sv)
JP (1) JPS5264279A (sv)
BE (1) BE848345A (sv)
CA (1) CA1064164A (sv)
DE (1) DE2652253C2 (sv)
ES (1) ES453471A1 (sv)
FR (1) FR2332615A1 (sv)
GB (1) GB1562095A (sv)
IT (1) IT1064386B (sv)
NL (1) NL176818C (sv)
SE (1) SE428614B (sv)

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NL7706802A (nl) * 1977-06-21 1978-12-27 Philips Nv Werkwijze voor het vervaardigen van een half- geleiderinrichting en halfgeleiderinrichting vervaardigd met behulp van de werkwijze.
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US4198250A (en) * 1979-02-05 1980-04-15 Intel Corporation Shadow masking process for forming source and drain regions for field-effect transistors and like regions
US4231811A (en) * 1979-09-13 1980-11-04 Intel Corporation Variable thickness self-aligned photoresist process
US5202574A (en) * 1980-05-02 1993-04-13 Texas Instruments Incorporated Semiconductor having improved interlevel conductor insulation
US4356623A (en) * 1980-09-15 1982-11-02 Texas Instruments Incorporated Fabrication of submicron semiconductor devices
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
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US4472874A (en) * 1981-06-10 1984-09-25 Tokyo Shibaura Denki Kabushiki Kaisha Method of forming planar isolation regions having field inversion regions
US4601095A (en) * 1981-10-27 1986-07-22 Sumitomo Electric Industries, Ltd. Process for fabricating a Schottky-barrier gate field effect transistor
US4585342A (en) * 1984-06-29 1986-04-29 International Business Machines Corporation System for real-time monitoring the characteristics, variations and alignment errors of lithography structures
IT1214805B (it) * 1984-08-21 1990-01-18 Ates Componenti Elettron Spositivi a semiconduttore con giunprocesso per la fabbricazione di dizioni planari a concentrazione di carica variabile e ad altissima tensione di breakdown
US4821094A (en) * 1985-11-08 1989-04-11 Lockheed Missiles & Space Company, Inc. Gate alignment procedure in fabricating semiconductor devices
DE3602461A1 (de) * 1986-01-28 1987-07-30 Telefunken Electronic Gmbh Verfahren zum herstellen eines sperrschicht-feldeffekttransistors
US4728617A (en) * 1986-11-04 1988-03-01 Intel Corporation Method of fabricating a MOSFET with graded source and drain regions
JPS63182860A (ja) * 1987-01-26 1988-07-28 Toshiba Corp 半導体装置とその製造方法
US4933295A (en) * 1987-05-08 1990-06-12 Raytheon Company Method of forming a bipolar transistor having closely spaced device regions
US4871684A (en) * 1987-10-29 1989-10-03 International Business Machines Corporation Self-aligned polysilicon emitter and contact structure for high performance bipolar transistors
US5171718A (en) * 1987-11-27 1992-12-15 Sony Corporation Method for forming a fine pattern by using a patterned resist layer
US4818714A (en) * 1987-12-02 1989-04-04 Advanced Micro Devices, Inc. Method of making a high performance MOS device having LDD regions with graded junctions
US5015595A (en) * 1988-09-09 1991-05-14 Advanced Micro Devices, Inc. Method of making a high performance MOS device having both P- and N-LDD regions using single photoresist mask
US5064773A (en) * 1988-12-27 1991-11-12 Raytheon Company Method of forming bipolar transistor having closely spaced device regions
EP0394597A1 (en) * 1989-04-28 1990-10-31 International Business Machines Corporation Follow-up System for Monitoring the Etching Process in an RIE Equipment and its Application to Producing High-resolution and Reproducible Patterns
US5223914A (en) * 1989-04-28 1993-06-29 International Business Machines Corporation Follow-up system for etch process monitoring
KR960000225B1 (ko) * 1991-08-26 1996-01-03 가부시키가이샤 한도오따이 에네루기 겐큐쇼 절연게이트형 반도체장치의 제작방법
US5272095A (en) * 1992-03-18 1993-12-21 Research Triangle Institute Method of manufacturing heterojunction transistors with self-aligned metal contacts
US5318916A (en) * 1992-07-31 1994-06-07 Research Triangle Institute Symmetric self-aligned processing
TW297142B (sv) 1993-09-20 1997-02-01 Handotai Energy Kenkyusho Kk
US6777763B1 (en) 1993-10-01 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for fabricating the same
JP3030368B2 (ja) 1993-10-01 2000-04-10 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
US5795830A (en) * 1995-06-06 1998-08-18 International Business Machines Corporation Reducing pitch with continuously adjustable line and space dimensions
US6232048B1 (en) 1996-12-31 2001-05-15 Advanced Micro Devices Method for preparing narrow photoresist lines
US6150072A (en) * 1997-08-22 2000-11-21 Siemens Microelectronics, Inc. Method of manufacturing a shallow trench isolation structure for a semiconductor device
US6069046A (en) * 1997-11-26 2000-05-30 Advanced Micro Devices, Inc. Transistor fabrication employing implantation of dopant into junctions without subjecting sidewall surfaces of a gate conductor to ion bombardment
US6121155A (en) * 1998-12-04 2000-09-19 Advanced Micro Devices Integrated circuit fabrication critical dimension control using self-limiting resist etch
WO2000034437A2 (en) * 1998-12-08 2000-06-15 Merck & Co., Inc. Inhibitors of prenyl-protein transferase
US6444536B2 (en) * 1999-07-08 2002-09-03 Agere Systems Guardian Corp. Method for fabricating bipolar transistors
US6376308B1 (en) * 2000-01-19 2002-04-23 Advanced Micro Devices, Inc. Process for fabricating an EEPROM device having a pocket substrate region
US6168993B1 (en) * 2000-01-19 2001-01-02 Advanced Micro Devices, Inc. Process for fabricating a semiconductor device having a graded junction
US6255147B1 (en) * 2000-01-31 2001-07-03 Advanced Micro Devices, Inc. Silicon on insulator circuit structure with extra narrow field transistors and method of forming same
US6828259B2 (en) 2001-03-28 2004-12-07 Advanced Micro Devices, Inc. Enhanced transistor gate using E-beam radiation
US6589709B1 (en) 2001-03-28 2003-07-08 Advanced Micro Devices, Inc. Process for preventing deformation of patterned photoresist features
US6815359B2 (en) * 2001-03-28 2004-11-09 Advanced Micro Devices, Inc. Process for improving the etch stability of ultra-thin photoresist
US6716571B2 (en) * 2001-03-28 2004-04-06 Advanced Micro Devices, Inc. Selective photoresist hardening to facilitate lateral trimming
US6774365B2 (en) 2001-03-28 2004-08-10 Advanced Micro Devices, Inc. SEM inspection and analysis of patterned photoresist features
JP2004533110A (ja) * 2001-03-28 2004-10-28 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Ｅビーム放射を使用した、改良されたトランジスタゲート
US6630288B2 (en) 2001-03-28 2003-10-07 Advanced Micro Devices, Inc. Process for forming sub-lithographic photoresist features by modification of the photoresist surface
US6653231B2 (en) 2001-03-28 2003-11-25 Advanced Micro Devices, Inc. Process for reducing the critical dimensions of integrated circuit device features
US6573165B2 (en) * 2001-07-06 2003-06-03 Texas Instruments Incorporated Method of providing polysilicon spacer for implantation
US7179752B2 (en) * 2001-07-10 2007-02-20 Tokyo Electron Limited Dry etching method
US20030092281A1 (en) * 2001-11-13 2003-05-15 Chartered Semiconductors Manufactured Limited Method for organic barc and photoresist trimming process
US6586303B2 (en) * 2001-12-05 2003-07-01 United Microelectronics Corp. Method for fabricating a mask ROM
KR100486111B1 (ko) * 2002-07-10 2005-04-29 매그나칩 반도체 유한회사 반도체소자의 소자분리막 제조방법
KR100559994B1 (ko) * 2003-08-08 2006-03-13 동부아남반도체 주식회사 측벽 방식을 이용한 플래시 메모리의 플로팅 게이트 형성방법
US7288829B2 (en) * 2004-11-10 2007-10-30 International Business Machines Corporation Bipolar transistor with self-aligned retrograde extrinsic base implant profile and self-aligned silicide
FR3030876B1 (fr) 2014-12-22 2017-12-15 Commissariat Energie Atomique Procede de realisation de motifs
US12194607B2 (en) 2018-10-17 2025-01-14 Kyocera Senco Industrial Tools, Inc. Working cylinder for power tool with piston lubricating system
CN120221397A (zh) 2023-12-26 2025-06-27 达尔科技股份有限公司 半导体结构的制造方法

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US3592707A (en) * 1968-06-17 1971-07-13 Bell Telephone Labor Inc Precision masking using silicon nitride and silicon oxide
US3816198A (en) * 1969-09-22 1974-06-11 G Babcock Selective plasma etching of organic materials employing photolithographic techniques
US3649393A (en) * 1970-06-12 1972-03-14 Ibm Variable depth etching of film layers using variable exposures of photoresists
US3890176A (en) * 1972-08-18 1975-06-17 Gen Electric Method for removing photoresist from substrate
US3940288A (en) * 1973-05-16 1976-02-24 Fujitsu Limited Method of making a semiconductor device
SE405526B (sv) * 1973-07-16 1978-12-11 Western Electric Co Transistor och sett for dess tillverkning
JPS5034175A (sv) * 1973-07-27 1975-04-02

Also Published As

Publication number Publication date
FR2332615B1 (sv) 1980-09-12
US3997367A (en) 1976-12-14
NL176818C (nl) 1985-06-03
ES453471A1 (es) 1977-11-16
DE2652253C2 (de) 1982-06-03
JPS5724938B2 (sv) 1982-05-26
JPS5264279A (en) 1977-05-27
CA1064164A (en) 1979-10-09
SE428614B (sv) 1983-07-11
FR2332615A1 (fr) 1977-06-17
IT1064386B (it) 1985-02-18
DE2652253A1 (de) 1977-06-02
BE848345A (fr) 1977-03-16
NL7612850A (nl) 1977-05-24
GB1562095A (en) 1980-03-05
NL176818B (nl) 1985-01-02

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