SG43722A1 - Computer interface circuit - Google Patents

Computer interface circuit

Info

Publication number: SG43722A1
Authority: SG; Singapore
Prior art keywords: interface circuit; computer interface; computer; circuit; interface
Prior art date: 1989-11-13

Application number

SG1996000201A

Other languages

English (en)

Inventor

Serafin Jose Eleazar Garcia Jr

Douglas Roderick Chisholm

Dean Alan Kalman

Russell Stephen Padgett

Robert Dean Yoder

Original Assignee

Ibm

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1989-11-13

Filing date

1990-11-08

Publication date

1997-11-14

1990-11-08 Application filed by Ibm filed Critical Ibm

1997-11-14 Publication of SG43722A1 publication Critical patent/SG43722A1/en

Links

Classifications

- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Landscapes

Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
Physics & Mathematics (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Computer Hardware Design (AREA)
Software Systems (AREA)
Bus Control (AREA)
Information Transfer Systems (AREA)

SG1996000201A 1989-11-13 1990-11-08 Computer interface circuit SG43722A1 (en)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
US07/434,385 US5119480A (en)	1989-11-13	1989-11-13	Bus master interface circuit with transparent preemption of a data transfer operation

Publications (1)

Publication Number	Publication Date
SG43722A1 true SG43722A1 (en)	1997-11-14

Family

ID=23724015

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
SG1996000201A SG43722A1 (en)	1989-11-13	1990-11-08	Computer interface circuit

Country Status (12)

Country	Link
US (1)	US5119480A (de)
EP (1)	EP0428330A3 (de)
JP (1)	JPH077374B2 (de)
KR (1)	KR930008039B1 (de)
CN (1)	CN1020815C (de)
AU (1)	AU638495B2 (de)
BR (1)	BR9005632A (de)
CA (1)	CA2026737C (de)
DE (1)	DE4035837A1 (de)
MY (1)	MY104505A (de)
NZ (1)	NZ235801A (de)
SG (1)	SG43722A1 (de)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5379381A (en) *	1991-08-12	1995-01-03	Stratus Computer, Inc.	System using separate transfer circuits for performing different transfer operations respectively and scanning I/O devices status upon absence of both operations
CZ383292A3 (en) *	1992-02-18	1994-03-16	Koninkl Philips Electronics Nv	Method of testing electronic circuits and an integrated circuit tested in such a manner
US5596749A (en) *	1992-09-21	1997-01-21	Texas Instruments Incorporated	Arbitration request sequencer
US5535333A (en) *	1993-03-30	1996-07-09	International Business Machines Corporation	Adapter for interleaving second data with first data already transferred between first device and second device without having to arbitrate for ownership of communications channel
WO1995034861A1 (en) *	1994-06-14	1995-12-21	Unisys Corporation	High speed deadlock free bridge circuit
JPH10133998A (ja) *	1996-11-05	1998-05-22	Canon Inc	データ処理方法とその方法を用いた記録装置
US6055583A (en) *	1997-03-27	2000-04-25	Mitsubishi Semiconductor America, Inc.	DMA controller with semaphore communication protocol
JPH10283329A (ja) *	1997-04-02	1998-10-23	Matsushita Electric Ind Co Ltd	メモリ排他制御方法
US6691257B1 (en)	2000-04-13	2004-02-10	Stratus Technologies Bermuda Ltd.	Fault-tolerant maintenance bus protocol and method for using the same
US6687851B1 (en)	2000-04-13	2004-02-03	Stratus Technologies Bermuda Ltd.	Method and system for upgrading fault-tolerant systems
US6820213B1 (en)	2000-04-13	2004-11-16	Stratus Technologies Bermuda, Ltd.	Fault-tolerant computer system with voter delay buffer
US6633996B1 (en)	2000-04-13	2003-10-14	Stratus Technologies Bermuda Ltd.	Fault-tolerant maintenance bus architecture
US6708283B1 (en)	2000-04-13	2004-03-16	Stratus Technologies, Bermuda Ltd.	System and method for operating a system with redundant peripheral bus controllers
US6735715B1 (en)	2000-04-13	2004-05-11	Stratus Technologies Bermuda Ltd.	System and method for operating a SCSI bus with redundant SCSI adaptors
US6901481B2 (en)	2000-04-14	2005-05-31	Stratus Technologies Bermuda Ltd.	Method and apparatus for storing transactional information in persistent memory
US6862689B2 (en)	2001-04-12	2005-03-01	Stratus Technologies Bermuda Ltd.	Method and apparatus for managing session information
US6802022B1 (en)	2000-04-14	2004-10-05	Stratus Technologies Bermuda Ltd.	Maintenance of consistent, redundant mass storage images
US6948010B2 (en)	2000-12-20	2005-09-20	Stratus Technologies Bermuda Ltd.	Method and apparatus for efficiently moving portions of a memory block
US6886171B2 (en)	2001-02-20	2005-04-26	Stratus Technologies Bermuda Ltd.	Caching for I/O virtual address translation and validation using device drivers
US6766479B2 (en)	2001-02-28	2004-07-20	Stratus Technologies Bermuda, Ltd.	Apparatus and methods for identifying bus protocol violations
US6766413B2 (en)	2001-03-01	2004-07-20	Stratus Technologies Bermuda Ltd.	Systems and methods for caching with file-level granularity
US6874102B2 (en)	2001-03-05	2005-03-29	Stratus Technologies Bermuda Ltd.	Coordinated recalibration of high bandwidth memories in a multiprocessor computer
US7065672B2 (en)	2001-03-28	2006-06-20	Stratus Technologies Bermuda Ltd.	Apparatus and methods for fault-tolerant computing using a switching fabric
US6996750B2 (en)	2001-05-31	2006-02-07	Stratus Technologies Bermuda Ltd.	Methods and apparatus for computer bus error termination
JP2005078161A (ja) *	2003-08-28	2005-03-24	Canon Inc	記録装置
US7043590B2 (en) *	2004-05-28	2006-05-09	Realtek Semiconductor Corp.	Interface apparatus using single driver, computer system including interface apparatus using single driver, and related method
US10380022B2 (en)	2011-07-28	2019-08-13	Netlist, Inc.	Hybrid memory module and system and method of operating the same
US10198350B2 (en)	2011-07-28	2019-02-05	Netlist, Inc.	Memory module having volatile and non-volatile memory subsystems and method of operation
US10838646B2 (en)	2011-07-28	2020-11-17	Netlist, Inc.	Method and apparatus for presearching stored data
CN103313459A (zh) *	2012-03-13	2013-09-18	鸿富锦精密工业（深圳）有限公司	指示灯控制装置
WO2015070110A2 (en)	2013-11-07	2015-05-14	Netlist, Inc.	Hybrid memory module and system and method of operating the same
US11182284B2 (en)	2013-11-07	2021-11-23	Netlist, Inc.	Memory module having volatile and non-volatile memory subsystems and method of operation
US10248328B2 (en)	2013-11-07	2019-04-02	Netlist, Inc.	Direct data move between DRAM and storage on a memory module
CN112540730B (zh) *	2020-12-14	2022-02-08	无锡众星微系统技术有限公司	可动态重构的dma阵列

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS503237A (de) *	1973-05-11	1975-01-14
US4270167A (en) *	1978-06-30	1981-05-26	Intel Corporation	Apparatus and method for cooperative and concurrent coprocessing of digital information
US4620278A (en) *	1983-08-29	1986-10-28	Sperry Corporation	Distributed bus arbitration according each bus user the ability to inhibit all new requests to arbitrate the bus, or to cancel its own pending request, and according the highest priority user the ability to stop the bus
US4777591A (en) *	1984-01-03	1988-10-11	Texas Instruments Incorporated	Microprocessor with integrated CPU, RAM, timer, and bus arbiter for data communications systems
JPH0690700B2 (ja) *	1984-05-31	1994-11-14	富士通株式会社	半導体集積回路
US4837677A (en) *	1985-06-14	1989-06-06	International Business Machines Corporation	Multiple port service expansion adapter for a communications controller
JPS62154045A (ja) *	1985-12-27	1987-07-09	Hitachi Ltd	バス調停方式
JPS6398755A (ja) *	1986-10-16	1988-04-30	Fujitsu Ltd	ダイレクトメモリアクセス制御装置
US4959782A (en) *	1986-10-29	1990-09-25	United Technologies Corporation	Access arbitration for an input-output controller
US4901226A (en) *	1987-12-07	1990-02-13	Bull Hn Information Systems Inc.	Inter and intra priority resolution network for an asynchronous bus system
JPH01277928A (ja) *	1988-04-30	1989-11-08	Oki Electric Ind Co Ltd	印刷装置
US4935868A (en) *	1988-11-28	1990-06-19	Ncr Corporation	Multiple port bus interface controller with slave bus

1989
- 1989-11-13 US US07/434,385 patent/US5119480A/en not_active Expired - Fee Related
1990
- 1990-10-02 CA CA002026737A patent/CA2026737C/en not_active Expired - Fee Related
- 1990-10-15 AU AU64556/90A patent/AU638495B2/en not_active Ceased
- 1990-10-17 JP JP2276573A patent/JPH077374B2/ja not_active Expired - Lifetime
- 1990-10-24 NZ NZ235801A patent/NZ235801A/en unknown
- 1990-10-29 MY MYPI90001890A patent/MY104505A/en unknown
- 1990-11-07 BR BR909005632A patent/BR9005632A/pt unknown
- 1990-11-08 EP EP19900312210 patent/EP0428330A3/en not_active Ceased
- 1990-11-08 SG SG1996000201A patent/SG43722A1/en unknown
- 1990-11-09 CN CN90109035A patent/CN1020815C/zh not_active Expired - Fee Related
- 1990-11-09 KR KR1019900018082A patent/KR930008039B1/ko not_active Expired - Fee Related
- 1990-11-10 DE DE4035837A patent/DE4035837A1/de not_active Ceased

Also Published As

Publication number	Publication date
CN1051994A (zh)	1991-06-05
US5119480A (en)	1992-06-02
JPH03160545A (ja)	1991-07-10
DE4035837A1 (de)	1991-05-16
EP0428330A3 (en)	1992-11-04
AU6455690A (en)	1991-05-16
CN1020815C (zh)	1993-05-19
CA2026737C (en)	1996-01-23
CA2026737A1 (en)	1991-05-14
EP0428330A2 (de)	1991-05-22
MY104505A (en)	1994-04-30
KR930008039B1 (ko)	1993-08-25
AU638495B2 (en)	1993-07-01
JPH077374B2 (ja)	1995-01-30
KR910010335A (ko)	1991-06-29
NZ235801A (en)	1994-01-26
BR9005632A (pt)	1991-09-17

Publication	Publication Date	Title
EP0428330A3 (en)	1992-11-04	Computer interface circuit
GB2226922B (en)	1992-05-27	Circuit
GB8904211D0 (en)	1989-04-12	Curve computer
KR970002390B1 (en)	1997-03-05	Serial data receiving circuit
EP0428261A3 (en)	1992-01-29	Computer user interface
AU106405S (en)	1990-01-08	Computer
EP0416331A3 (en)	1991-07-03	Line computer
AU107450S (en)	1990-04-26	Computer
AU108409S (en)	1990-07-30	Computer
AU106367S (en)	1990-01-02	Computer
AU105091S (en)	1989-09-15	An electronic computer
EP0421351A3 (en)	1991-10-30	An electronic computer
AU110242S (en)	1991-02-07	Computer
EP0340720A3 (en)	1990-03-28	Interface circuit
AU111383S (en)	1991-06-26	Electronic computer
EP0273360A3 (en)	1989-09-06	Electronic computer
EP0431570A3 (en)	1993-02-24	Logical circuit
GB8709835D0 (en)	1987-05-28	Touch-control anit-burglar circuit
GB2211006B (en)	1992-06-03	Interface circuit
EP0420409A3 (en)	1992-09-16	Interface circuit
GB2214335B (en)	1991-10-23	Interface board for computers
GB8925463D0 (en)	1989-12-28	Computers
AU111351S (en)	1991-06-17	An electronic computer
AU109717S (en)	1990-11-30	An electronic computer
AU109718S (en)	1990-11-30	An electronic computer