SU492000A1 - Memory device with blocking faulty cells - Google Patents

Description

one

It is known that its device with blocking faulty cells contains an external drive, a permanent drive whose inputs are connected to the address decoder, and outputs to the first inputs of the register, the second inputs of which are connected to the outputs of the first additional storage device, and the outputs to the error detection unit , the address register connected to the address decoder, the comparison unit, and the second additional drive.

A disadvantage of the known memory device is that it is not capable of automatically restoring its operability in case of accidental faults and failures of memory elements arising during operation of the device.

The described device differs from the known one in that it contains an address code converter, the inputs of which are connected to the output of the address register, the outputs to the inputs of the external storage device, the outputs of which are connected to the third inputs of the register and the inputs of the first additional storage device, are connected to one of the address register outputs.

These differences can improve the reliability of the device.

The drawing shows a block diagram of the proposed device.

The device contains an external drive 1, the converter 2 address code, register 3

addresses with inputs 4, address decoder 5, fixed drive 6, register 7, error detection block 8, control block 9, first additional drive 10, second additional drive 11, serving

for storing the code of the faulty address, block 12 comparison.

The outputs of the decoder 5 are connected to the inputs of the accumulator 6, the outputs of which are connected to the first inputs of the register 7. The outputs of the register 7 are connected to the external information buses 13 and the inputs of the block 8, the output of which is connected to the input of the control block 9. The outputs of the accumulator 10 are connected to the second inputs of the register 7. The outputs of the accumulator 11 are connected to the inputs of the block 12, the output of which is connected to the input of the block 9; the output of block 9 is connected to the input of accumulator 1, whose outputs are connected to the third inputs of register 7 and information inputs of accumulator 10. Transmitter 2 outputs are connected to address inputs of accumulator 1. Control unit 9 outputs are connected to inputs of registers 3, 7 and accumulators 10, 11 a also to the external bus 14. Outputs 15 first

groups of bits of the register 3, defining

group of words of accumulator 6, connected to inputs of converter 2, decoder 5 and address inputs of drives 10 and I. Outputs 16 of the second group of register bits 3, define the word in the group of words, connected to inputs of converter 2, decoder 5, block 12 and information formati drive inputs 11.

The operation of the device is as follows.

According to the address code received on register 3, the decoder 5 selects from the accumulator 6 a corresponding group of words and a specific word in it, which is sent to register 7 by the command from block 9. At the same time, according to the code of the first group of bits of the address code, the accumulator x 10 and And are selected by one word that correspond to the group of words selected in the accumulator 6.

If, when reading, the error detection unit 8 did not generate an error signal, the correct information was read and it goes to the external buses 13.

If block 8 generates an error signal to control block 9, the latter sets the re-read mode from accumulator 6. If block 8 now does not detect an error, it is read that the first read was a failure, and information is output to external buses 13.

However, if, when re-reading, block 8 again generates an error signal, then control block 9 implements the following program: sends a signal to access drive 1, which, according to the address code on register 3, passed through code converter 2, drive 1 issues correct information for a 6 cell that failed in the primary drive. This information enters the pegister 3 and, but the signal from block 9 is recorded in the corresponding cell of accumulator 10. At the same time, the code of the second group of bits 16 of address register 7 is entered into accumulator 11.

So there is an automatic entry of codes of faulty addresses in the drive 11 and the corresponding serviceable information in the drive 10.

If now the access to the drive 6 occurs at the faulty address, then the block

12 compares a signal to this in block 9, which blocks the reception of information from the main storage device 6 and permits - from the storage device 10.

When issuing information to external tires

13, block 9 sends an end of turn signal to bus 14.

Claims (1)

Invention Formula A memory device with blocking faulty cells, containing an external tip, a fixed tip, the inputs of which are connected to the address decoder, and the outputs to the first inputs of the register, the second inputs of which are connected to the outputs of the first additional storage device, and the outputs to the error detection unit, the address register connected to the address decoder, the comparison unit, and the second additional drive, characterized in that, in order to increase the reliability of the device, it contains an address code converter, the inputs of which are connected to the output the address register, the outputs to the inputs of the external nozzle, the outputs of which are connected to the third inputs of the register and the inputs of the first additional nozzle, the inputs of the second additional storage device are connected with one of the outputs of the address register.