經濟部智慧財產局員工消費合作社印Sli 乂 41狐3 6 6 A7 ^ -—— 57 五'發明說明（1) [發明領域] 本發明係有關於一種積體電路封裝技術’特別是有關 於一種積艘電路封裝方法，其可用來封裝一光感式積雜電 路晶片，例如為一影像感應器（image sens〇r),其特點在於 可防止導線架上產生溢膝現象（flash)，並可使得所痒接上 的晶片導線具有更佳之焊接性（b〇ndabiltiy) e [發明背景】 ^積體電路封裝技術可將一或多個積體電路晶片封裝於 單之模組之中，以便易於將此些積體電路晶片整合至電 路板上。—般之積體電路晶片大都是封裝於不透光之封裝 膠體之中《•然而對於光感式積體電路晶片而言由於其感 光面須能接收到外部之光線，否則其將無法正常作用因 此光感式積體電路晶片的封裝方法通常不同於一般之積體 電路晶片的封裝方法。 目前己有許多的專利技術可用來封裝光感式積體電路 晶片，例如美國專利第5,070,041號及美國專利第 5,523,608 號，等等 β 美國專利第5,07〇,〇41號揭露了 一種單晶片型光感式 積體電路晶片的封裝方法’其製程步驟將於以下配合第 至1D圖作簡略之敘述。 請首先參閱第1Α囷，美國專利第5 070,04ΐ號所揭露 之封裝方法的第一個步驟為預製一導線架11()，其具有一 晶片座部分111及一導腳部分112。為防止後續之製程於 導線架110之晶片座部分ln及導腳部分112内側上產生 本&張尺度適用1f7國國家標準（CNSM4規格（21〇 X 297公釐)----^ 1 15990 --------1---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 2 A7 B7 五、發明說明（2 ) 溢膠現像’其解決方法為在此些部位上預先塗佈上一聚合 物塗佈層120。 請接著參閱第1B圖，下一個步驟為進行一模鑄製程 (molding process) ’藉此形成一上部封裝膠體121及—下 部封裝勝體122。上部封裝膠體121具有一中央空穴部分， 用以作為黏晶之處β 於此模鑄製程中’用以形成上部封裝膠體121及下部 封裝膠體122的封裝材料會溢濺於導線架11()之晶片座部 分111及導腳部分112的内側上’亦即溢濺於預塗佈之聚 合物塗佈層120之上（溢膠部分如標號13〇所指之處）。由 於此些部位已預先塗佈上聚合物塗佈層12〇，因此可接著 使用一特殊之溶劑’將聚合物塗佈層丨2〇連同其上之溢膠 部分130 —起清洗掉，藉此而除去溢膠部分丨3〇。 請接著參閱第1C圖’下一個步驟為進行一黏晶製程， 用以將一光感式積體電路晶片140黏貼至導線架11〇的晶 片座部分in上。接著將下部封裝膠體122放置於一加熱 塊（heat block) 150上，以此方式來進行一導線焊接製程， 藉此焊接上一導線組160，以將光感式積體電路晶片14〇 電性藕接至導線架11〇之導腳部分112的内側上。 請接著參閱接著第1D圖’下一個步驟為進行一加蓋 片製程（lidding process) ’用以將一透光蓋片17〇固接至上 部封裝膠體121的中央空穴部分的開口上。此即完成一單 晶片型光感式積趙電路封裝結構的製造。 然而上述之積體電路封裝方法卻有以下二項缺點。第 本紙張尺度適用中圉國家標聿（CNS)A4規格（210 15990 --------------裝--------訂---1-----線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 443 6 6 A7 B7 五、發明說明（3 ) 一項缺點為形成聚合物塗佈層120及後績之溶劑清洗程 序，其程序頗為繁複且須使用昂貴之器材，致使製造成本 頗高。第二項缺點則為導線焊接製程t所用的加熱塊150 係接觸至下部封裝膠體122的底面，而非直接接觸至導線 架110，因此會使得加熱塊150上的熱能不能以最有效之 方式傳送至導線架110上，致使所焊接上的導線組160僅 具有勉強可接受之焊接性。 美國專利第5,523,608號揭露了 一種雙晶片型光感式 積體電路晶片的封裝方法，其製程步驟將於以下配合第2A 至2D圏作簡略之敘述。 請參閱第2A圖，美國專利第5,523,608號所揭露之封 裝方法的第一個步驟為預製一導線架210，其具有一晶片 座部分211及一導腳部分212。接著即進行一第一黏晶製 程，藉以將一第一積體電路晶片241黏貼至導線架210之 晶片座部分211的背面上。接著進行一第一導線焊接製 程’用以利用一第一導線組261將第一積體電路晶片241 電性藕接至導線架210之導腳部分212的背面上。 請接著參閱第2B圖，下一個步棘令為進行一模镑製 程，藉以形成一上部封裝膠體221及一下部封裝膠體222。 上部封裝膠體221具有一中央空穴部分，用以作為第二黏 晶之處；而下部封裝膠體222則完全包覆第一積趙電路晶 片 241。 於上述之模鑄製程令，用以形成上部封裝谬艘221及 下部封裝膠體222的封裝材料會溢滅於導線架21〇之晶片 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 15990 -I -----I------ ------ 1 1 訂·-----— II *5^ (請先閱讀背面之注意事項再填寫本頁) 3 A7Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, Sli 乂 41 fox 3 6 6 A7 ^ ----- 57 Five 'Description of Invention (1) [Field of Invention] The present invention relates to an integrated circuit packaging technology' especially to a The Jaeger-Packer circuit packaging method can be used to package a light-sensing hybrid circuit chip, such as an image sensor (sensor), which is characterized by preventing flashover from occurring on the lead frame, and Make the iterated chip wires have better solderability. [Background of the invention] ^ Integrated circuit packaging technology can package one or more integrated circuit chips in a single module, so as to facilitate These integrated circuit chips are integrated on a circuit board. —Most integrated circuit chips are mostly packaged in opaque packaging gels. “However, for light-sensing integrated circuit chips, the photosensitive surface must be able to receive external light, otherwise it will not function properly. Therefore, the packaging method of the photosensitive integrated circuit chip is usually different from the general packaging method of the integrated circuit chip. Currently, there are many patented technologies that can be used to package light-sensitive integrated circuit chips, such as US Patent No. 5,070,041 and US Patent No. 5,523,608, etc. β US Patent No. 5,07〇, 〇41 discloses a single chip The method of packaging a light-sensing integrated circuit chip 'its process steps will be briefly described below with reference to Figures 1D. Please refer to No. 1A 所, the first step of the packaging method disclosed in U.S. Patent No. 5,070,04ΐ is to prefabricate a lead frame 11 (), which has a wafer base portion 111 and a lead pin portion 112. In order to prevent subsequent processes from occurring on the inside of the chip holder portion ln and the guide pin portion 112 of the lead frame 110, the & Zhang scale is applicable to the national standard of 1f7 (CNSM4 specification (21 × X 297 mm) ---- 1 15990 -------- 1 --------- Line (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 A7 B7 V. Invention Description ( 2) The appearance of overflowing glue 'The solution is to pre-coat a polymer coating layer 120 on these parts. Please refer to FIG. 1B, the next step is to perform a molding process. An upper encapsulating colloid 121 and a lower encapsulating body 122 are formed. The upper encapsulating colloid 121 has a central cavity portion as a place for sticking crystals β. In this molding process, 'the upper encapsulating colloid 121 and the lower encapsulation are formed. The encapsulation material of the gel 122 will spill on the inside of the chip holder portion 111 and the lead pin portion 112 of the lead frame 11 (), that is, it will spill on the pre-coated polymer coating layer 120 (the overflow portion such as Where the number 13 refers). Since these areas have been pre-coated with polymer The polymer coating layer 12 can be subsequently washed with a special solvent '20 and the overflow portion 130 thereon, thereby removing the overflow portion 3 '. Please refer to Figure 1C 'The next step is to perform a die-bonding process to attach a light-sensitive integrated circuit chip 140 to the chip holder portion in of the lead frame 110. Then, the lower packaging gel 122 is placed on a heating block ( heat block) 150, a wire welding process is performed in this way, thereby welding a wire group 160 to electrically connect the light-sensitive integrated circuit chip 14o to the lead portion 112 of the lead frame 11o Please refer to FIG. 1D for the next step, 'The next step is to perform a lidding process' for fixing a light-transmissive cover sheet 170 to the central cavity portion of the upper encapsulant 121. On the opening. This completes the manufacture of a single-chip light-sensing integrated circuit packaging structure. However, the above-mentioned integrated circuit packaging method has the following two disadvantages. This paper standard applies to the Chinese National Standard (CNS) A4 Specifications (210 15990 ------ -------- Equipment -------- Order --- 1 ----- line (please read the precautions on the back before filling this page) System 443 6 6 A7 B7 V. Description of the invention (3) A disadvantage is the solvent cleaning procedure for forming the polymer coating layer 120 and subsequent performance. The procedure is quite complicated and requires expensive equipment, resulting in high manufacturing costs. The second disadvantage is that the heating block 150 used in the wire bonding process t is in contact with the bottom surface of the lower packaging gel 122, rather than directly contacting the lead frame 110. Therefore, the thermal energy on the heating block 150 cannot be transmitted in the most efficient way. To the lead frame 110, so that the soldered lead group 160 has only barely acceptable solderability. U.S. Patent No. 5,523,608 discloses a packaging method for a dual-chip photo-sensing integrated circuit chip. The manufacturing steps will be briefly described below in conjunction with 2A to 2D. Referring to FIG. 2A, the first step of the packaging method disclosed in U.S. Patent No. 5,523,608 is to prefabricate a lead frame 210 having a wafer base portion 211 and a lead pin portion 212. Then, a first die bonding process is performed, whereby a first integrated circuit chip 241 is adhered to the back surface of the chip holder portion 211 of the lead frame 210. Next, a first wire bonding process is performed to electrically connect the first integrated circuit chip 241 to the back of the lead portion 212 of the lead frame 210 using a first wire group 261. Please refer to FIG. 2B. The next step is to perform a mold process to form an upper package gel 221 and a lower package gel 222. The upper encapsulation gel 221 has a central cavity portion for the second sticking place; and the lower encapsulation gel 222 completely covers the first product circuit chip 241. In the above-mentioned mold casting process order, the packaging materials used to form the upper package 221 and the lower package gel 222 will overflow the wafer of the lead frame 21. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297). Mm) 15990 -I ----- I ------ ------ 1 1 Order · -----— II * 5 ^ (Please read the notes on the back before filling in this page ) 3 A7
五、發明說明（4 ) 經濟部智慧財產局員工消費合作社印製 座部分211及導腳部分212内側上（溢膠部分如標號23〇所 指之處）。為了清除此溢膠部分23〇，其解決方法為利用一 噴洗器231進行一喷洗程序（bUst)，藉由高速噴液將溢膠 部分230喷洗掉。 請接著參閱第2C圖，下一個步驊為進行一第二黏晶 製程，藉以將一第二積體電路晶片242(光感式積體電路晶 片）黏貼至導線架210之晶片座部分211的正面上。 接著將下部封裝膠體222放置於一加熱塊250上，以 此方式來進行一第二導線焊接製程，藉此焊接上一第二導 線組262’以將光感式積體電路晶片242電性藕接至導線 架210之導腳部分212内側的正面上。 請接著參閱第2D圖，下一個步驟為進行一加蓋片製 程’用以將一透光蓋片270固接至上部封裝膠體221的中 央空穴部分的開口上。此即完成一雙晶片型光感式積體電 路封裝結構的製造》 然而上述之積體電路封裝方法亦有以下二項缺點。第 —項缺點為用以清除溢膠部分230的喷洗程序，其程序亦 頗為繁複且需使用昂貴之器材，致使製造成本頗高。第二 項缺點則為第二導線焊接製程中所用的加熱塊250係接觸 至下部封裝膠體222的底面，而非直接接觸至導線架210, 因此會使得加熱塊250上的熱能不能以最有效之方式傳送 至導線架210上，致使所焊接上的第二導線組262僅具有 勉強可接受之焊接性。 [發明概述] 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 15990 -------------裝 — 訂---------線 (請先閱讀背面之注意事項再填寫本頁) 4443 6 6 A7 B7 五、發明說明（5 ) 蓉於以上所述習知技術之缺點，本發明之主要目的便 是在於提供一種新的光感式積體電路封裝方法，其可防止 上述之溢膠現象》 本發明之另一目的在於提供一種新的光感式積體電路 封裝方法’其可讓導線焊接製程令所用之加熱塊直接接觸 至導線架，以使得所焊接上的導線具有更佳之焊接性。 根據以上所述之目的，本發明提供了一種新穎之光感 式積體電路封裝方法。本發明之積體電路封裝方法利用一 特製之模具組’包括一上插入式模具及一下插入式模具， 來緊密地夾持導線架上會產生溢膠現象之部位，藉此來防 止此些部位產生溢膠現象’因此無需如習知技術般地採用 高成本之清洗程序來去除溢勝》此外，本發明之積艘電路 封裝方法於導線焊接製程中’可讓加熱塊直接接觸至導線 架’形成直接之熱傳導接觸’因此可使加熱塊上的熱能較 習知技術更為有效地傳送至導線架上，使得所焊接上的導 線組具有更佳之焊接性。本發明之積體電路封裝方法因此 較習知技術具有更進步之實用性。 [圖式簡述] 為讓本發明之上述和其它目的、特徵、和優點能更明 顯易懂，下文將舉本發明之較佳實施例，並配合所附囷式， 詳細說明本發明之實質技術内容。所附圖式之内容簡述如 下： 第1Α至1D圖（習知技術）為剖面示意圓，其用以說明 —習知之單晶片型光感式積艘電路封裝方法中的各個步 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 15990 «3· (請先閱讀背面之注意事項再填寫本頁) -45V. Description of the invention (4) Printed on the inside of the seat part 211 and the guide leg part 212 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (the plastic overflow part is as indicated by reference numeral 230). In order to remove the overflow portion 23, the solution is to use a sprayer 231 to perform a spray washing process (bUst), and spray-wash the overflow portion 230 by high-speed spraying. Please refer to FIG. 2C. The next step is to perform a second die-bonding process, so that a second integrated circuit chip 242 (photosensitive integrated circuit chip) is adhered to the chip holder portion 211 of the lead frame 210. On the front. Next, the lower encapsulant 222 is placed on a heating block 250 to perform a second wire welding process in this way, thereby welding a second wire group 262 'to electrically photo-integrate the integrated circuit chip 242. It is connected to the front side of the inner side of the guide leg portion 212 of the lead frame 210. Please refer to FIG. 2D. The next step is to perform a capping process to fix a transparent cover sheet 270 to the opening in the central cavity portion of the upper packaging gel 221. This completes the manufacture of a dual-chip light-sensitive integrated circuit packaging structure. However, the above-mentioned integrated circuit packaging method also has the following two disadvantages. The first disadvantage is the spray cleaning procedure for removing the glue overflow portion 230. The procedure is quite complicated and requires expensive equipment, resulting in high manufacturing costs. The second disadvantage is that the heating block 250 used in the second wire welding process is in contact with the bottom surface of the lower packaging gel 222, rather than directly contacting the lead frame 210, so the thermal energy on the heating block 250 cannot be used most effectively. The method is transferred to the lead frame 210, so that the soldered second wire group 262 has only barely acceptable solderability. [Summary of the invention] This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 15990 ------------- Package-Order --------- Line (Please read the notes on the back before filling this page) 4443 6 6 A7 B7 V. Description of the invention (5) The disadvantages of the conventional technology described above, the main purpose of the present invention is to provide a new light sense Method for packaging integrated circuits, which can prevent the above-mentioned glue overflow phenomenon. Another object of the present invention is to provide a new photo-sensing integrated circuit packaging method, which allows the wire bonding process to directly contact the heating block used in the process. Lead frame, so that the soldered wires have better solderability. According to the above-mentioned object, the present invention provides a novel light-sensing integrated circuit packaging method. The integrated circuit packaging method of the present invention uses a special mold set 'including an upper insert mold and a lower insert mold to tightly clamp the parts on the lead frame where the glue overflow phenomenon occurs, thereby preventing these parts The occurrence of glue overflow phenomenon 'so there is no need to use high-cost cleaning procedures to remove overflow wins as in the conventional technology.' In addition, the method of packaging the circuit board of the present invention in the wire bonding process 'allows the heating block to directly contact the lead frame' Forming a direct thermal conduction contact 'therefore allows the heat energy on the heating block to be transferred to the lead frame more efficiently than conventional techniques, so that the soldered wire group has better solderability. The integrated circuit packaging method of the present invention is therefore more practical than conventional techniques. [Brief Description of the Drawings] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes preferred embodiments of the present invention and the accompanying formulae to explain the essence of the present invention in detail. Technical content. The contents of the drawings are briefly described as follows: Figures 1A to 1D (conventional technology) are schematic circle cross-sections, which are used to explain the steps of the conventional single-chip light-sensing shipbuilding circuit packaging method. Standards are applicable to China National Standard (CNS) A4 (210 X 297 mm) 15990 «3 · (Please read the precautions on the back before filling this page) -45
T 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（6 驟； 經 濟 部 智 慧 財 產 局 消 f 合 社 印 tl 第2A至2D圖（¾知技術）為剖面示意圖，其用以說明 一習知之雙晶片型光感式積體電路封裝方*中的各個少 驟； 第3A至3E圖為剖面示意圖，其用以說明本發明之耪 體電路封裝方法的第一實施例令，用來製造一單晶片蜇光 感式積想電路封裝結構中的各個步雜； 第4A至4F圈為剖面示意圖，其用以說明本發明之積 體電路封裝方法的第二實施例中，用來製造〆雙晶片塑光 感式積體電路封裝結構中的各個步碌。 [圖式之標號] Π0 導線架 導線架Π0之晶片座部分 導線架110之導腳部分 聚合物塗佈層 上部封裝膠體 下部封裝膠體 溢膠部分 光感式積體電路晶片 加熱塊（heat block) 導線組 透光蓋片 導線架 導線架210之晶片座部分T Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (6 steps; Consumer Council of Intellectual Property of the Ministry of Economic Affairs f. Respective steps in a conventional dual-chip light-sensing integrated circuit packaging method * Figures 3A to 3E are schematic cross-sectional views for explaining a first embodiment of the method for packaging a body circuit of the present invention. To manufacture the various steps in a single-chip photo-sensing integrated circuit packaging structure. Circles 4A to 4F are schematic cross-sectional views for explaining a second embodiment of the integrated circuit packaging method of the present invention. Various steps in manufacturing a 晶片 two-chip plastic light-sensing integrated circuit package structure. [Number of the figure] Π0 Lead frame Lead frame Π0 Chip holder part Lead frame part of the lead frame 110 Polymer coating layer Upper packaging gel Lower package gel overflow part Photosensitive integrated circuit chip heat block (wire block) Transparent cover sheet Lead frame Lead frame 210 Wafer base portion
I請 先 聞 讀 背 面 之 '注 意 事 項 再 填λ 寫裝 本 · J 訂 111 112 120 121 122 130 140 150 160 170 210 211 線 本紙張义度適用中國國家標準（CNS)A4規格（210 X 297公釐_> 6 15990 A7 4443 6 6 B7_ 五、發明說明（7 ) 212 導線架210之導腳部分 221 上部封裝膠體 (請先間讀背面之注意事項再填寫本頁) 222 下部封裝膠體 230 溢膠部分 23 1 嘴洗器（blaster) 241 第一積體電路晶片 242 第二積體電路晶片（光感式積體電路晶片） 250 加熱塊 261 第一導線組 262 第二導線組 270 透光蓋片 310 導線架 311 導線架310之晶片座部分 312 導線架310之導腳部分 320 模具組 321 上插入式模具 321a 第一空穴結構 經濟部智慧財產局員工消費合作社印製 322 下插入式模具 322a 第二空穴結構 331 上封裝邊牆結構 332 下封裝邊牆結構 340 光感式積體電路晶片 350 加熱塊 360 導線組 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 7 15990 經濟部智慧財產局員工消費合作社印製 A7 _B7_ 五、發明說明（1 2 ) 370 底部封裝膠體 380 透光蓋片 410 導線架 411 導線架410之晶片座部分 412 導線架410之導腳部分 420 模具組 421 上插入式模具 421a 第一空穴結構 422 下插入式模具 422a 第二空穴結構 431 上封裝邊牆結構 432 下封裝邊牆結構 441 第一積體電路晶片 442 第二積體電路晶片（光感式積體電路晶片） 451 第一加熱塊 452 第二加熱塊 461 第一導線組 462 第二導線組 470 底部封裝膠體 480 透光蓋片 [發明實施例詳細說明] 以下將分別配合第3A至3E圊及第4A至4F圖分別詳 細揭露說明本發明之積體電路封裝方法的二個實施例。 第一實施例f第3A至3E圖） -------------裝--------訂---------線 <請先閲讀背面之注意事項再填寫本頁) 1 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公釐） 2 15990 -443 6 6 A7 —______B7 五'發明說明（9 ) 以下將配合第3A至3E圖詳細揭露說明本發明之積體 (請先《讀背面之注意事項再填寫本頁) 電路封裝方法之第一實施例。於此實施例令，本發明之積 艘電路封裝方法係用來製造一單晶片型之光感式積體電路 封裝結構。 請首先參閲第3A圖，此實施例之第一個步驟為預製 一導線架310及一特別設計之模具組320 ^導線架310具 有一晶片座部分311及一導腳部分312»模具組320包括 二個插入式模具（inserted mold): —上插入式模具321及一 下插入式模具322;其中上插入式模具321之下表面上形 成有一第一空穴結構321a，而下插入式模具322之上表面 上則形成有一第二空穴結構322a(此二個空穴結構將於後 續之製程中用以分別形成二個封裝邊牆結構）。 經濟部智慧財產局員工消費合作社印製 請接著參閱第3B圈’下一個步驟為將導線架31〇夾 固於上插入式模具321與下插入式模具322之間，使得導 線架310之晶片座部分311及導腳部分312之内端均被大 致緊密地夾固於上插入式模具321與下插入式模具322之 間，並使得第一以及第二空穴結構321a、322a互相對齊至 導線架310之導腳部分312中的一特定區段，接著便可進 行一模鑄製程，用以將一封裝材料，例如為樹脂，填入至 第一及第二空穴結構321a、322a之t。 請接著參閱第3C圈’下一個步驟為移除上插入式模 具321及下插人式模具322。此模轉製程完成之後，填入 至第一空穴結構321a中的封裝材料即形成一上封裝邊牆 結構33卜而填入至第二空穴結構322a令的封裝材料則形I Please read the 'Precautions on the back side' and then fill in the λ paperback. J order 111 112 120 121 122 130 140 150 160 170 210 211 The meaning of thread paper is applicable to China National Standard (CNS) A4 (210 X 297) _ ≫ 6 15990 A7 4443 6 6 B7_ V. Description of the invention (7) 212 Lead frame part of lead frame 210 221 Upper package gel (please read the precautions on the back before filling this page) 222 Lower package gel 230 Overflow Glue part 23 1 Mouthwasher (blaster) 241 First integrated circuit wafer 242 Second integrated circuit wafer (photosensitive integrated circuit wafer) 250 Heating block 261 First lead set 262 Second lead set 270 Transparent cover Sheet 310 Lead frame 311 Wafer base portion of lead frame 310 312 Lead frame portion of lead frame 320 Mold set 321 Upper plug-in mold 321a First cavity structure Ministry of Economic Affairs Intellectual Property Bureau Employee Consumption Cooperative printed 322 Lower plug-in mold 322a The second cavity structure 331 the upper package side wall structure 332 the lower package side wall structure 340 light-sensing integrated circuit chip 350 heating block 360 wire group This paper size applies to Chinese National Standard (CNS) A4 specification (2 10 X 297 mm) 7 15990 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _B7_ V. Description of the Invention (1 2) 370 Bottom encapsulation gel 380 Transparent cover sheet 410 Lead frame 411 Lead frame part 410 Wafer part 412 Lead Guide part 420 of frame 410 Mold set 421 Upper insert mold 421a First cavity structure 422 Lower insert mold 422a Second cavity structure 431 Upper package side wall structure 432 Lower package side wall structure 441 First integrated circuit chip 442 Second integrated circuit wafer (photosensitive integrated circuit wafer) 451 First heating block 452 Second heating block 461 First wire group 462 Second wire group 470 Underside encapsulation gel 480 Transparent cover sheet [Detailed embodiment of the invention Explanation] In the following, two embodiments illustrating the integrated circuit packaging method of the present invention will be disclosed in detail in conjunction with Figures 3A to 3E 圊 and Figures 4A to 4F respectively. First embodiment f Figures 3A to 3E) ---- --------- Installation -------- Order --------- line < Please read the precautions on the back before filling this page) 1 This paper size is applicable to country t National Standard (CNS) A4 Specification (210 X 297 mm) 2 15990 -443 6 6 A7 —______ B7 Five 'Invention Description (9) The first embodiment of the circuit packaging method will be disclosed in detail below with reference to Figures 3A to 3E (please read the "Cautions on the back side before filling this page"). In this embodiment, the package circuit packaging method of the present invention is used to manufacture a single-chip light-sensitive integrated circuit package structure. Please refer to FIG. 3A first. The first step of this embodiment is to prefabricate a lead frame 310 and a specially designed mold set 320. ^ The lead frame 310 has a wafer base portion 311 and a guide leg portion 312 »mold set 320. Including two insert molds:-upper insert mold 321 and lower insert mold 322; wherein a first cavity structure 321a is formed on the lower surface of the upper insert mold 321, and the lower insert mold 322 A second cavity structure 322a is formed on the upper surface (these two cavity structures will be used to form two packaging side wall structures respectively in subsequent processes). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to circle 3B. The next step is to clamp the lead frame 31 ° between the upper insert mold 321 and the lower insert mold 322, so that the wafer holder of the lead frame 310 The inner ends of the portion 311 and the guide pin portion 312 are approximately tightly clamped between the upper insertion mold 321 and the lower insertion mold 322, and the first and second cavity structures 321a and 322a are aligned with each other to the lead frame. A specific section of the guide pin portion 312 of 310 can then be subjected to a molding process to fill a packaging material, such as a resin, into the first and second cavity structures 321a, 322a. Please refer to circle 3C '. The next step is to remove the upper insert mold 321 and the lower insert mold 322. After this mold conversion process is completed, the packaging material filled into the first cavity structure 321a forms an upper packaging side wall structure 33 and the packaging material filled into the second cavity structure 322a is shaped.
本紙張尺度邮t賴家辟(CNS)A4規格(210 X 297公FT 9 15990 五、發明說明（的 成一下封裝邊牆結構332。 (請先闓讀背面之注意事項再填寫本頁> 本發明的一項特點即在於藉由上述第3B圖所示之爽 固動作，亦即將導線架310之晶片座部分3n及導腳部分 312内端緊密地夾固於上插入式模具32ι與下插入式模具 322之間，因此於模鑄製程進行中，可使得此些部位不會 被封裝材料所觸及到，亦即此些部位上不會殘留有溢膠。 請接著參閱第3D圈，下一個步驟為進行一黏晶製程， 用以將一光感式積體電路晶片34〇黏貼至導線架31〇之晶 片座部分311的正面上。 接著將下封裝邊牆結構332放置於一加熱塊350上， 以此方式來進行一導線焊接製程’藉此銲接上一導線組 360,以將光感式積體電路晶片34〇電性藕接至導線架31〇 之導腳部分312的内端上。於此步驟中，加熱塊35〇可經 由下封裝邊牆結構332的中央空穴部分而直接接觸至導線 架310之晶片座部分311及導腳部分312的内端，形成直 接之熱傳導接觸。導線焊接製程完成之後，接著將加熱塊 350移除。 經濟部智慧財產局員工消費合作杜印製 本發明的另一項特點即在於藉由下封裝邊牆結構332 的_央空穴部分，即可讓加熱塊35〇與導線架31〇之晶片 座部分311及導腳部分312内端形成直接之熱傳導接觸’ 因此於上述之導線焊接製程進行中，可讓加熱塊35〇上的 熱能較習知技術更為有效地傳送至導線架3 1〇之晶片座部 分311及導腳部分312，使得導線組36〇具有更佳之焊接 性。 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 10 15990 4443 6 6 經濟部智慧財產局員工消費合作杜印製 A7 B7 五、發明說明（π ) 請接著參閱第3E圖，下一個步驟為將環氧樹脂（ep〇xy) 或矽鲖（silicone)填入至下封裝邊牆結構332的中央空穴部 分中’藉此而形成一底部封裝膠體3 70，用以包覆導線架 31〇之晶片座部分311及導腳部分312内端的背面。 最後一個步驟為進行一加蓋片製程（lidding process)’藉此將一透光蓋片380固接至上封裝邊牆結構 331的中央空穴部分的開口上β此即完成一單晶片型光感 式積體電路封裝結構的製造》 由以上之說明可知’本發明之積體電路封裝方法可防 止導線架310之晶片座部分311及導腳部分312的内端上 殘留模鑄製程中所用之模料，因此無需如習知技術般地採 用高成本之清洗程序來去除溢膠。此外，本發明於導線焊 接製程中，可讓加熱塊350直接接觸至導線架310之晶片 座部分311及導腳部分312的内端，形成直接之熱傳導接 觸’因此可使加熱塊350上的熱能較習知技術更為有效地 傳送至導線架3 10之晶片座部分311及導腳部分3 12的内 端上’使得所焊接上的導線組360具有更佳之烊接性。本 發明因此較習知技術具有更進步之實用性。 蓋實施例f竿4 A I 4F圈） 以下將配合第4A至4F圓詳細揭露說明本發明之積體 電路封裝方法之第二實施例。於此實施例中，本發明之積 艘電路封裝方法係用以製造一雙晶片型之光感式積體電路 封裝結構。 請首先參閱第4A圖，此實施例之第一個步驟為預製 -----I----- 裝 - ----—訂---— II--•線 (請先Μ讀背面之注意事項再填寫本頁) 本4張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 11 15990 A7 A7 經濟部智慧財產局員工消費合作杜印製 12 五、發明說明（Π ) ~導線架410及一特別設計之模具組42〇。導線架41〇具 明片座部；7 411及一導腳部分412。模具組420包括 —上插入式模具421及一下插入式模具422;其中上插入 式模具421之下表面上形成有一第一空穴結構42ia，而下 插入式模具422之上表面上則形成有一第二空穴結構 422a(此二個空六結構係於後續之製程中用以分別形成二 個封裝邊牆結構）^ 請接著參閲第4B圖，下一個步驟為將導線架41〇夾 固於上插入式模具421與下插入式模具4 22之間，使得導 線架410之晶片座部分411及導腳部分412内端均被大致 緊密地夹固於上插入式模具421與下插入式模具422之 間，並使得第一以及第二空穴結構421a、422a互相對齊至 導線架410之導腳部分412中的一特定區段。接著便可進 行一模鑄製程，用以將一封裝材料，例如為樹脂，填入至 第一及第二空穴結構421a、422a之中。 請接著參閱第4C圖，下一個步驟為移除上插入式模 具421及下插入式模具422。此模鑄製程完成之後’填入 至第一空穴結構421a中的封裝材料即形成一上封裝邊牆 結構431，而填入至第二空穴結構422a书的封裝材料則形 成一下封裝邊牆結構432。 本發明的一項特點即在於藉由上述第4B圖所示之夹 固動作，亦即將導線架410之晶片座部分411及導腳部分 412内端緊密地夾固於上插入式模具421與下插入式模具 422之間’因此於模鑄製程進行中，可使得此些部位不會 表紙；綱㈣鮮鮮(CNS)A4規格⑵〇 X 297公髮) —--- 15990 IF n It n I IT .^r n 訂---------線 (請先閱讀背面之注意事項再填寫本頁) 4443 66 A7 ___B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（13) 被封裝材料所觸及到，亦即此些部位上不會殘留有溢膠β 請接著參閲第4D圏，下一個步驟為將整個半成品之 封裝結構體翻轉成正面朝下，以此方式來進行一第一黏晶 製程’用以將一第一積體電路晶片44〗（非光感式之積體電 路晶片）黏貼至導線架410之晶片座部分411的背面上。 接著將上封裝邊牆結構431放置於一第一加熱塊451 上’以此方式來進行一第一導線焊接製程，藉此焊接上一 第一導線組461 ’以將第一積體電路晶片441電性藕接至 導線架410之導腳部分412内端的背面上》於此步驟中， 第一加熱塊451可經由上封裝邊牆結構43!的中央空穴部 分而直接接觸至導線架410之晶片座部分411及導腳部分 412内端的正面，形成直接之熱傳導接觸。第一導線谭接 製程完成之後’接著將加熱塊451移除。 本發明的另一項特點即在於藉由上封裝邊牆結構431 的中央空六部分’可讓第一加熱塊451舆導線架410之晶 片座部分411及導腳部分412内端的正面形成直接之熱傳 導接觸’因此於第一導線焊接製程進行中，可讓第一加熱 塊451上的熱能較習知技術更為有效地傳送至導線架410 之晶>1座部分411及導腳部分412,使得第一導線組461 具有更佳之焊接性。 請接著參閱第4Ε圖’下一個步称為將整個半成品之 封裝結構體再回復成正面朝上，以此方式來進行一第二黏 晶製程，用以將一第二積體電路晶片442(光感式積體電路 晶片）黏貼至導線架410之晶片座部分411的正面上β {請先閱讀背面之注意事項再填寫本頁) ί Γ 良 泰紙張尺度適用中_國家標準（CNS)A4規格（210 x 297公釐） 13 15990 經濟部智慧財產局員工消費合作社印製 007 aV·#? ^ 14 A7 B7 五、發明說明（14) 接著將下封裝邊牆結構432放置於一第二加熱塊452 上’以此方式來進行一第二導線焊接製程，藉此焊接上一 第二導線組462 ’以將第二積體電路晶片442電性藕接至 導線架410之導腳部分412内端的正面上3於此步驟中， 第二加熱塊452可經由下封裝邊牆結構432的中央空穴部 分而直接接觸至導線架41〇之導腳部分412内端的背面， 形成直接之熱傳導接觸。第二導線焊接製程完成之後，接 著即將第二加熱塊452移除。 本發明的再一項特點即在於藉由下封裝邊牆結構432 的t央空穴部分，可讓第二加熱塊452與導線架41〇之晶 片座部分411及導腳部分412内端的背面形成直接之熱傳 導接觸，因此於第二導線焊接製程進行中’可讓第二加熱 塊452上的熱能較習知技術更為有效地傳送至導線架 之BB片座部分411及導腳部分412，使得第二導線組462 具有更佳之焊接性。 請接著參閱第4F圖，下一個步驟為將環氧樹脂或矽 酮填入至下封裝邊牆結構432的中央空穴部分藉此而形 成一底部封裝膠體470’用以包覆第一積趙電路晶片441 及導線架410之晶片座部分411及導腳部分412内端的背 面 β 最後一個步驟為進行一加蓋片製程，用以 片480固接至上封裝邊踏結構431的中央空穴部分的開口 上。此即完成-雙晶片型光感式積體電路封裝結構的製 造。 本紙張&度適用中關家標準（CNS)AU計；ηη 15990 -------------裝- ------訂--------線 (請先閱讀背面之注意事項再填寫本頁) 4443 6 6 A7 B7 五、發明說明（”） 由以上之說明可知*本發明之積體電路封裝方法可防 止導線架410之晶片座部分411及導腳部分412的内端上 殘留模鑄製程中所用之模料，因此無需如習知技術般地採 用高成本之清洗程序來去除溢膠《•此外，本發明於第一及 第二導線焊接製程中’均可讓加熱塊451、452與導線架 410之導腳部分412的内端形成直接之熱傳導接觸，因此 可使加熱塊451、452上的熱能較習知技術更為有效地傳送 至導線架410上*使得所焊接上的導線组461、462均具有 更佳之焊接性》本發明因此較習知技術具有更進步之實用 性。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之實質技術内容的範圍。本發明之實質技術内容 係廣義地定義於下述之申請專利範圍中。任何他人所完成 之技術實體’若是與下述之f請專利範圍所定義者為完全 相同、或是為一種等效之變更，均將被視為涵蓋於此專利 範圍之中。 I------------ - ί I ----訂·---- ί <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用t國國家楳準（CNS)A4規格（210 X 297公爱） 15 15990This paper standard post Lai Jiapi (CNS) A4 specifications (210 X 297 male FT 9 15990) V. Description of the invention (to complete the package side wall structure 332. (Please read the precautions on the back before filling out this page > A feature of the present invention is that the inner ends of the chip holder portion 3n and the guide pin portion 312 of the lead frame 310 are tightly clamped to the upper insert mold 32m and the lower portion by the cool-solid action shown in the above FIG. 3B. Inserted between the molds 322, so during the molding process, these parts will not be touched by the packaging material, that is, there will be no overflow of glue on these parts. Please refer to the 3D circle, the next One step is to perform a die-bonding process for adhering a light-sensitive integrated circuit chip 34o to the front surface of the chip holder portion 311 of the lead frame 31o. Next, the lower package side wall structure 332 is placed on a heating block. In 350, a wire welding process is performed in this way to thereby solder a wire group 360 to electrically connect the light-sensitive integrated circuit chip 34o to the inner end of the lead portion 312 of the lead frame 31o. Upper. In this step, the heating block 35 can be passed through the lower package. The central cavity portion of the side wall structure 332 directly contacts the inner ends of the wafer base portion 311 and the lead pin portion 312 of the lead frame 310 to form a direct thermal conductive contact. After the wire welding process is completed, the heating block 350 is then removed. The consumer property cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs Du printed another feature of the present invention is that by encapsulating the central cavity portion of the side wall structure 332, the heating block 35o and the lead frame 31o can be used. The inner ends of the portion 311 and the guide pin portion 312 form a direct thermal conduction contact. Therefore, during the above-mentioned wire welding process, the heat energy on the heating block 35 can be more efficiently transmitted to the lead frame 3 1 than the conventional technology. The chip holder part 311 and the guide pin part 312 make the wire group 36 ° have better solderability. This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 10 15990 4443 6 6 Intellectual Property Bureau of the Ministry of Economic Affairs Printed by A7 B7 by employee consumption cooperation 5. Description of invention (π) Please refer to Figure 3E. The next step is to fill epoxy resin (ep〇xy) or silicon wafer (silicon) into the bottom package side wall. In the central cavity portion of the structure 332, a bottom encapsulant 3 70 is formed to cover the back surface of the inner end of the chip holder portion 311 and the lead pin portion 312 of the lead frame 31. The last step is to perform a capping The "lidding process" is used to fix a light-transmissive cover sheet 380 to the opening of the central cavity portion of the upper package side wall structure 331. This completes the manufacture of a single-chip light-sensitive integrated circuit package structure 》 From the above description, it can be known that the integrated circuit packaging method of the present invention can prevent the mold material used in the molding process from remaining on the inner ends of the chip holder portion 311 and the lead pin portion 312 of the lead frame 310, so there is no need for conventional techniques High cost cleaning procedures are generally used to remove spills. In addition, in the wire welding process of the present invention, the heating block 350 can directly contact the inner ends of the wafer base portion 311 and the guide leg portion 312 of the lead frame 310 to form a direct thermal conductive contact. Therefore, the thermal energy on the heating block 350 can be made. The transfer to the inner ends of the chip holder portion 311 and the lead pin portion 3 12 of the lead frame 3 10 is more effective than the conventional technique, so that the soldered lead group 360 has better connection. The present invention therefore has more advanced practicability than conventional techniques. Covering the embodiment (4A, 4F, and 4F circles) The following describes the second embodiment of the integrated circuit packaging method of the present invention in detail with the 4A to 4F circles. In this embodiment, the package circuit packaging method of the present invention is used to manufacture a dual-chip type light-sensitive integrated circuit package structure. Please refer to FIG. 4A first, the first step of this embodiment is prefabrication ----- I ----- installation------order ----II-• line (please read first Note on the back, please fill in this page again.) The 4 scales are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 11 15990 A7 A7 Printed by the staff of Intellectual Property Bureau of the Ministry of Economic Affairs. Π) ~ lead frame 410 and a specially designed mold set 42. The lead frame 41 〇 has a pedestal seat portion; 7 411 and a guide leg portion 412. The mold set 420 includes an upper insert mold 421 and a lower insert mold 422; wherein a first cavity structure 42ia is formed on the lower surface of the upper insert mold 421, and a first cavity structure is formed on the upper surface of the lower insert mold 422. Two-cavity structure 422a (these two air-six structures are used to form two packaging side wall structures in subsequent processes) ^ Please refer to FIG. 4B. The next step is to clamp the lead frame 41o to Between the upper insert mold 421 and the lower insert mold 4 22, the inner ends of the wafer holder portion 411 and the guide pin portion 412 of the lead frame 410 are approximately tightly clamped between the upper insert mold 421 and the lower insert mold 422. The first and second cavity structures 421 a and 422 a are aligned with each other to a specific section in the guide pin portion 412 of the lead frame 410. Then, a mold casting process can be performed to fill a packaging material, such as a resin, into the first and second cavity structures 421a, 422a. Please refer to FIG. 4C. The next step is to remove the upper insert mold 421 and the lower insert mold 422. After the molding process is completed, the packaging material filled in the first cavity structure 421a forms an upper packaging side wall structure 431, and the packaging material filled in the second cavity structure 422a forms a packaging side wall. Structure 432. A feature of the present invention is that the inner ends of the wafer holder portion 411 and the guide pin portion 412 of the lead frame 410 are tightly clamped to the upper insert mold 421 and the lower portion by the clamping action shown in FIG. 4B. Between the plug-in molds 422 ', therefore, during the casting process, these parts will not be covered with paper; Gangxinxian (CNS) A4 size ⑵〇X 297 issued) ----- 15990 IF n It n I IT. ^ Rn Order --------- line (please read the notes on the back before filling this page) 4443 66 A7 ___B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (13) Touched by the packaging material, that is, there will be no overflow glue on these parts. Please refer to Section 4D 圏. The next step is to turn the entire semi-finished packaging structure to face down. The first die bonding process is used to adhere a first integrated circuit chip 44 (a non-photosensitive integrated circuit chip) to the back surface of the chip holder portion 411 of the lead frame 410. Next, the upper package side wall structure 431 is placed on a first heating block 451 'to perform a first wire welding process in this way, thereby welding a first wire group 461' to place the first integrated circuit chip 441 It is electrically connected to the back of the inner end of the guide leg portion 412 of the lead frame 410. In this step, the first heating block 451 can directly contact the lead frame 410 through the central cavity portion of the upper package side wall structure 43! The front faces of the inner ends of the wafer holder portion 411 and the guide pin portion 412 make direct thermal conductive contact. After completion of the first wire tan process, the heating block 451 is removed. Another feature of the present invention is that the front surface of the inner end of the chip holder portion 411 and the guide pin portion 412 of the first heating block 451 and the lead frame 410 can be directly formed by encapsulating the central hollow six portions of the side wall structure 431. 'Thermal conduction contact' therefore, during the first wire welding process, the heat energy on the first heating block 451 can be more efficiently transmitted to the crystal of the lead frame 410 than the conventional technology > 1 seat portion 411 and guide pin portion 412, As a result, the first lead set 461 has better solderability. Please refer to FIG. 4E. 'The next step is to restore the entire semi-finished package structure to the front side again. In this way, a second die bonding process is performed to use a second integrated circuit chip 442 ( Photosensitive integrated circuit chip) Adhered to the front side of the chip holder part 411 of the lead frame 410 β {Please read the precautions on the back side before filling out this page) ί Γ Liangtai paper size applicable _ National Standard (CNS) A4 (210 x 297 mm) 13 15990 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 007 aV · #? ^ 14 A7 B7 V. Description of the invention (14) The lower package side wall structure 432 is then placed on a second heating block 452 is used to perform a second wire welding process in this manner, thereby welding a second wire group 462 ′ to electrically connect the second integrated circuit chip 442 to the inner end of the lead portion 412 of the lead frame 410 On the front side, in this step, the second heating block 452 may directly contact the back surface of the inner end of the guide leg portion 412 of the lead frame 41 through the central cavity portion of the lower package side wall structure 432 to form a direct thermal conductive contact. After the second wire welding process is completed, the second heating block 452 is then removed. Another feature of the present invention is that the bottom surface of the central cavity portion of the side wall structure 432 can be used to form the second heating block 452 and the back surface of the chip holder portion 411 and the lead leg portion 412 of the lead frame 41. Direct thermal conduction contact, so during the second wire welding process, 'the heat energy on the second heating block 452 can be more effectively transmitted to the BB sheet base portion 411 and the guide leg portion 412 of the lead frame than the conventional technology, so that The second wire group 462 has better solderability. Please refer to FIG. 4F. The next step is to fill the central cavity portion of the lower package side wall structure 432 with epoxy resin or silicone to form a bottom package colloid 470 'to cover the first product. Circuit chip 441 and back surface of inner ends of chip holder portion 411 and lead pin portion 412 of lead frame 410 β The last step is to perform a capping process to fix chip 480 to the central cavity portion of upper package side step structure 431 On the opening. This completes the fabrication of a dual-chip photo-sensing integrated circuit package structure. The paper & degree applies to the Zhongguanjia Standard (CNS) AU meter; ηη 15990 ------------- installation------- order -------- line ( (Please read the precautions on the back before filling this page) 4443 6 6 A7 B7 V. Description of the invention (") From the above description, the integrated circuit packaging method of the present invention can prevent the chip holder portion 411 and the lead of the lead frame 410. The mold material used in the molding process remains on the inner end of the leg portion 412, so there is no need to use a high-cost cleaning procedure to remove the overflow glue as in the conventional technology. "In addition, the present invention is used for the first and second wire welding processes Both can make the heating blocks 451, 452 make direct thermal conduction contact with the inner end of the guide leg portion 412 of the lead frame 410, so that the heat energy on the heating blocks 451, 452 can be transmitted to the wire more effectively than the conventional technology On the frame 410 *, the soldered wire groups 461 and 462 have better solderability. The present invention therefore has more advanced practicability than the conventional technology. The above description is only a preferred embodiment of the present invention, and is not Used to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is Broadly defined in the scope of patent application below. Any technical entity 'completed by others' that is exactly the same as the definition of patent scope below or an equivalent change will be considered as Covered by the scope of this patent. I -------------ί I ---- Order · ---- ί < Please read the notes on the back before filling this page) Economy Printed by the Consumers' Cooperative of the Ministry of Intellectual Property Bureau, the paper size is applicable to the national standard of China (CNS) A4 (210 X 297 public love) 15 15990