US4611302A - Non-volatile data stores - Google Patents

Non-volatile data stores Download PDF

Info

Publication number
US4611302A
US4611302A US06/626,261 US62626184A US4611302A US 4611302 A US4611302 A US 4611302A US 62626184 A US62626184 A US 62626184A US 4611302 A US4611302 A US 4611302A
Authority
US
United States
Prior art keywords
power
storage means
volatile data
battery
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US06/626,261
Other languages
English (en)
Inventor
Charles P. Bockett-Pugh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gemalto Terminals Ltd
Original Assignee
Schlumberger Electronics UK Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Schlumberger Electronics UK Ltd filed Critical Schlumberger Electronics UK Ltd
Assigned to SCHLUMBERGER ELECTRONICS (U.K.) LIMITED, A CORP OF ENGLAND reassignment SCHLUMBERGER ELECTRONICS (U.K.) LIMITED, A CORP OF ENGLAND ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: BOCKETT-PUGH, CHARLES P.
Application granted granted Critical
Publication of US4611302A publication Critical patent/US4611302A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/141—Battery and back-up supplies

Definitions

  • This invention relates to non-volatile read/write data stores, that is to data stores the contents of which can be altered and which are capable of retaining data in the absence of the normal operating power supply.
  • CMOS random-access memory RAM
  • a typical CMOS RAM includes a control terminal to determine whether any given memory access operation is to read data from the memory or to write data into it.
  • a write operation is in many cases signified by a low (negative-going) signal on the control terminal, provided for example by connecting the terminal to the ground potential of the memory and the circuit containing it.
  • a non-volatile data store comprising volatile data storage means, power terminals for receiving power from a power source, and a battery for maintaining energisation of the storage means upon interruption of the power supply from the power source, the storage means having a control terminal for receiving a control signal of predetermined polarity to enable data transfer with the storage means, wherein a power input of the storage means and a power output of the battery, each having said predetermined polarity, are selectively connectable to the corresponding one of the power terminals, and are arranged to be disconnected therefrom upon interruption of the supply from the power source.
  • the battery has the additional effect of maintaining the disconnectable power input of the storage means (such as a CMOS RAM), whose potential defines a write control signal, at a potential several volts different from the circuit power terminal to which it is normally coupled. Accordingly, any spurious circuit operation which results in the potential of the circuit power terminal being applied to the read/write control terminal of the memory (and which could thus otherwise result in a spurious write operation) has no effect, since the write control terminal adopts a potential several volts different from that of the disconnectable power input of the memory, and thus does not enable a write operation.
  • the storage means such as a CMOS RAM
  • a CMOS RAM 10 has data and address lines 12, control lines 14 including a NOT-WRITE-ENABLE (WE*) line 16, a 0 V power line 18 and a +5 V power line 20.
  • WE* NOT-WRITE-ENABLE
  • the +5 V line 20 is coupled to a +5 V line 22 of the system containing the data store, and the 0 V line 18 is connected to the negative terminal of a 3.6 V rechargeable nickel-cadmium battery 24.
  • the positive terminal of this battery is coupled to the system +5 V line 22 via a resistor 26 and a diode 28 which provide trickle-charging for the battery 24 when the system +5 V line 22 is energised, and also via a diode 32 connected in parallel with the resistor 26 and diode 28 and in opposite polarity to the diode 28.
  • An electrolytic capacitor 34 is coupled across the power lines 18 and 20 of the RAM 10.
  • the RAM 0 V line 18 is connectable to the system 0 V (ground) line 36 via the collector-emitter circuit of an NPN transistor 38, the base of which is energised by the collector of a PNP transistor 40.
  • the emitter and base of this PNP transistor are coupled to the system +5 V line 22 by respective resistors 42 and 44, and the base is coupled to the system 0 V line 36 via a reverse-biased 3.3 V zener diode 46.
  • CMOS RAM requires several tens of milliamps of operating current, which must be conducted by the transistor 38, the component values are chosen to provide a base current of several milliamps.
  • the RAM 0 V line 18 is at virtually the same potential as the system 0 V line 36.
  • Logic 0 signals (at system 0 V potential) applied to the RAM lines 12 and 14 by circuitry elsewhere in the system, including write enable signals on the WE* line 16, therefore have their normal effect on the operation of the RAM 10.
  • the battery 24 is maintained charged by current flowing through the resistor 26 and diode 28.
  • the capacitor 34 is held charged to the full potential (+5 V) of the system power supply.
  • the capacitor 34 causes the voltage of the RAM 0 V line 18 to fall in step with that on the line 22.
  • the capacitor 34 also acts as a reservoir to provide current to the RAM 10 and to the transistor 38 (the base-collector junction of which becomes temporarily forward biassed as the voltage of the line 18 falls).
  • the voltage on line 18 continues to drop to several volts negative of the line 36, until the voltage of the supply line 22 has more or less stabilised. Thereafter the voltage of the line 18 slowly rises again, as the capacitor 34 discharges, until the voltage across the capacitor is low enough for the diode 32 to become forward-biassed by the battery 24, which then supplies current in place of the capacitor 34. At this point the voltage of the line 18 stabilises at a voltage, relative to the line 36, of around -3.2 V (3.6 V minus the 0.4 V drop across the diode 32 at a current of the order of 1 ⁇ A).
  • the zener diode 46 ensures that by the time this happens, the transistor 40, and thus the transistor 38, are fully turned off. Thus, even if the supply line 22 does not fall completely to zero, there is no current flow through the transistor 38 and the battery 24 only has to sustain the very small current requirement of the RAM 10.
  • any signal at the potential of the line 36 (which would normally be applied as a write enable signal to the WE* input 16) will in fact appear to be at a potential, relative the RAM ground line 18, of at least 2.4 V positive. As this is defined as an unambiguous logic high, it is ineffective to enable the RAM for writing.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Power Sources (AREA)
  • Static Random-Access Memory (AREA)
US06/626,261 1983-06-30 1984-06-29 Non-volatile data stores Expired - Fee Related US4611302A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8317747 1983-06-30
GB08317747A GB2142488B (en) 1983-06-30 1983-06-30 Non-volatile data stores

Publications (1)

Publication Number Publication Date
US4611302A true US4611302A (en) 1986-09-09

Family

ID=10545025

Family Applications (1)

Application Number Title Priority Date Filing Date
US06/626,261 Expired - Fee Related US4611302A (en) 1983-06-30 1984-06-29 Non-volatile data stores

Country Status (4)

Country Link
US (1) US4611302A (de)
EP (1) EP0130760A3 (de)
JP (1) JPS6074061A (de)
GB (1) GB2142488B (de)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4673824A (en) * 1986-03-03 1987-06-16 Tektronix, Inc. Power supply switch circuit
US4831595A (en) * 1987-05-06 1989-05-16 Hughes Aircraft Company Low voltage power down logic control circuit
US4874960A (en) * 1988-03-04 1989-10-17 Square D Company Programmable controller capacitor and battery backed ram memory board
US5058075A (en) * 1988-08-12 1991-10-15 Mitsubishi Denki Kabushiki Kaisha Battery circuit for an integrated circuit (IC) memory card
US5300765A (en) * 1990-03-19 1994-04-05 Mitsubishi Denki Kabushiki Kaisha Memory card with latch-up protection

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3704938A1 (de) * 1987-02-17 1988-08-25 Bosch Gmbh Robert Steuergeraet fuer brennkraftmaschinen
JPH02121193A (ja) * 1988-10-28 1990-05-09 Matsushita Electric Ind Co Ltd 不揮発性メモリー書込み制御装置
AT399621B (de) * 1990-10-22 1995-06-26 Vaillant Gmbh Netzausfallschaltung
PL2180118T3 (pl) 2008-10-21 2012-03-30 Sist Tecnicos De Encofrados Sa Ruchoma platforma do podtrzymywania szalunku do pionowych ścian i tym podobnych

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54149436A (en) * 1978-05-16 1979-11-22 Matsushita Electric Ind Co Ltd Memory protection circuit
EP0019222A1 (de) * 1979-05-15 1980-11-26 Mostek Corporation Schaltung zur elektrischen Verbindung eines flüchtigen Speichers mit einer Stromversorgungseingangsklemme
EP0051533A2 (de) * 1980-11-03 1982-05-12 FAIRCHILD CAMERA & INSTRUMENT CORPORATION MOS-Steuerschaltung einer Batteriereserveanlage für Mikrocomputer-Direktzugriffspeicher
WO1982004345A1 (en) * 1981-05-27 1982-12-09 Aswell Cecil James Power supply control for integrated circuit
US4399524A (en) * 1980-02-18 1983-08-16 Sharp Kabushiki Kaisha Memory protection system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3209704A1 (de) * 1982-03-12 1983-09-22 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur aufrechterhaltung von speicherinformationen von fluechtigen schreiblesespeichereinrichtungen bei betriebsspannungsausfall

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54149436A (en) * 1978-05-16 1979-11-22 Matsushita Electric Ind Co Ltd Memory protection circuit
EP0019222A1 (de) * 1979-05-15 1980-11-26 Mostek Corporation Schaltung zur elektrischen Verbindung eines flüchtigen Speichers mit einer Stromversorgungseingangsklemme
US4399524A (en) * 1980-02-18 1983-08-16 Sharp Kabushiki Kaisha Memory protection system
EP0051533A2 (de) * 1980-11-03 1982-05-12 FAIRCHILD CAMERA & INSTRUMENT CORPORATION MOS-Steuerschaltung einer Batteriereserveanlage für Mikrocomputer-Direktzugriffspeicher
WO1982004345A1 (en) * 1981-05-27 1982-12-09 Aswell Cecil James Power supply control for integrated circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4673824A (en) * 1986-03-03 1987-06-16 Tektronix, Inc. Power supply switch circuit
US4831595A (en) * 1987-05-06 1989-05-16 Hughes Aircraft Company Low voltage power down logic control circuit
US4874960A (en) * 1988-03-04 1989-10-17 Square D Company Programmable controller capacitor and battery backed ram memory board
US5058075A (en) * 1988-08-12 1991-10-15 Mitsubishi Denki Kabushiki Kaisha Battery circuit for an integrated circuit (IC) memory card
US5300765A (en) * 1990-03-19 1994-04-05 Mitsubishi Denki Kabushiki Kaisha Memory card with latch-up protection

Also Published As

Publication number Publication date
EP0130760A3 (de) 1988-03-23
GB8317747D0 (en) 1983-08-03
JPS6074061A (ja) 1985-04-26
GB2142488B (en) 1986-10-08
EP0130760A2 (de) 1985-01-09
GB2142488A (en) 1985-01-16

Similar Documents

Publication Publication Date Title
US4677311A (en) Power supply system for an electronic apparatus having memory
EP0440204B1 (de) Integrierte Halbleiterschaltungsanordnung mit einem Hauptleistungsanschluss und einem Sicherungsleistungsanschluss, die unabhängig voneinander sind
US4874960A (en) Programmable controller capacitor and battery backed ram memory board
US3980935A (en) Volatile memory support system
US4209710A (en) Battery back-up regulator
US4090255A (en) Circuit arrangement for operating a semiconductor memory system
US4611302A (en) Non-volatile data stores
US5357395A (en) Undervoltage protection circuit, system and method of operating same
US5118962A (en) Power supply backup circuit
WO1981002357A1 (en) Backup power circuit for biasing bit lines of a static semiconductor memory
US5852377A (en) Reset circuit for ensuring proper reset when used with decaying power supplies
WO1983001351A1 (en) Voltage regulation and battery dissipation limiter circuit
EP0868688B1 (de) Rücksetzstellungsschaltung zur sicherstellung der korrekten rücksetzstellung für den fall zusammenbrechender stromversorgung
EP0057556B1 (de) Statische Halbleiterspeicheranordnung
US5397935A (en) Bias current supplying circuit
US4764839A (en) Low voltage reset circuit
JP2548183B2 (ja) メモリ−カ−ド
JPS59127540A (ja) バツクアツプ用電源回路
KR950008457B1 (ko) 트랜지스터를 이용한 sram 백-업 회로
KR900008241Y1 (ko) 스태틱 램의 메모리 데이터 백업회로
JPS60229129A (ja) 停電補償回路
JPS6260437A (ja) 電源バツクアツプ回路
JPS595999B2 (ja) メモリ保護回路
JPS613221A (ja) メモリ回路の停電補償回路
JPH0546280A (ja) バツクアツプ回路

Legal Events

Date Code Title Description
AS Assignment

Owner name: SCHLUMBERGER ELECTRONICS (U.K.) LIMITED 124 VICTOR

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:BOCKETT-PUGH, CHARLES P.;REEL/FRAME:004368/0805

Effective date: 19850130

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
FP Lapsed due to failure to pay maintenance fee

Effective date: 19940914

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362