US5041894A - Integrated circuit with anti latch-up circuit in complementary MOS circuit technology - Google Patents

Integrated circuit with anti latch-up circuit in complementary MOS circuit technology Download PDF

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US5041894A
US5041894A US07/477,929 US47792990A US5041894A US 5041894 A US5041894 A US 5041894A US 47792990 A US47792990 A US 47792990A US 5041894 A US5041894 A US 5041894A
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transistor
terminal
conductivity type
circuit
well
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Werner Reczek
Wolfgang Pribyl
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Infineon Technologies AG
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Siemens AG
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention

Definitions

  • the invention is directed to an integrated circuit with anti latch-up circuit in complementary MOS circuit technology conforming to the preamble of patent claim 1.
  • parasitic pnpn paths between the supply voltage and the ground occur that are similar to a thyristor.
  • This parasitic four-layer structure can be ignited by disturbances, for example by current pulses or by over-shoots or under-shoots of the applied supply voltage at the semiconductor layers.
  • the switch from the normal condition into a highly conductive condition, i.e. the igniting of this four-layer structure, is referred to as latch-up.
  • the collector of the pnp bipolar transistor corresponds to the base of the npn bipolar transistor and the base of the pnp bipolar transistor corresponds to collector of the npn bipolar transistor.
  • This structure forms a four-layer diode having the layer sequence pnpn as in a thyristor. Given a positive bias of the semiconductor substrate, the pn-junction between the third and fourth semiconductor layers can be biased to such an extent in conducting direction that a current path arises between the said transistor terminals, this current path to be attributed to a parasitic thyristor effect within this four-layer structure. The current path also continues to be present after the dismantling of the positive substrate bias and can thermally overload the integrated circuit.
  • FIG. 3.6 on page 109 shows a complementary transistor pair in solid silicon with respect thereto, whereby FIG. 3.7c additionally illustrates the parasitic, lateral and vertical bipolar transistors that are of critical significance for the latch-up effect.
  • a third solution derives from the employment of a floating well-shaped semiconductor zone as described in the publication by H. P. Zappe et al, " Floating well CMOS and Latch-Up", IEDM 85, pages 517-520, 9 Dec. 1985.
  • the well-shaped semiconductor zone is connected to the "outside world" only via the parasitic source-drain pn-junctions of the MOS transistor lying in the well-shaped semiconductor zone, as a result whereof no base current can flow through the parasitic, vertical bipolar transistor.
  • the object of the invention is to specify a circuit of the species initially cited wherein the appearance of latch-up effects is largely avoided. This is inventively achieved by a fashioning of the circuit according to the characterizing part of patent claim 1.
  • Patent claims 2 through 7 are directed to preferred developments and improvements of the invention.
  • the advantage obtainable with the invention is particularly comprised therein that the circuit of the invention does not influence the circuit properties of the MOS transistors and the circuit of the invention is suitable both for well-shaped semiconductor zones having a fixed potential as well as for well-shaped semiconductor zones having a variable potential. Further, the space requirement for the circuit of the invention is extremely low since only one additional circuit element is required for it.
  • FIGS. 2, 4 and 5 of the drawing Two exemplary embodiments of the invention as well as a possible realization thereof are shown in FIGS. 2, 4 and 5 of the drawing and shall be set forth in greater detail below. Shown are:
  • FIG. 1 an equivalent circuit diagram of an output stage having bypass transistor
  • FIG. 2 a cross section through a CMOS output stage having CMOS output transistors, whereby the well-shaped semiconductor zone is connected to a fixed potential;
  • FIG. 3 an equivalent circuit diagram of a pn-channel MOS transistor wired as diode or as load element and having a bypass transistor;
  • FIG. 4 a cross section through a p-channel MOS transistor wired as diode or as load element and having a bypass transistor, whereby the well-shaped semiconductor zone is not connected to a fixed potential;
  • FIG. 5 a realization of a p-channel MOS transistor wired as diode or as load element and having a bypass transistor which conforms to the circuit recited in FIG. 3 and in FIG. 4.
  • FIG. 1 shows the equivalent circuit diagram of a CMOS output stage having a bypass transistor BT.
  • An existing post KL is thereby wired with the supply voltage V DD .
  • the CMOS output stage contains two series-connected, complementary field effect transistors T1 and T2, whereby the p-channel field effect transistor T1 has its source and substrate terminal applied to the supply voltage V DD and the n-channel field effect transistor T2 has its source terminal connected to the ground V ss .
  • the gate terminals G1, G2 of the p-channel field effect transistor T1 and of the n-channel field effect transistor T2 together form the input IN of the CMOS output stage, whereas the drain terminals of the p-channel field effect transistor T1 and of t he n-channel field effect transistor T2 are connected to the output OUT.
  • the substrate terminal of the n-channel field effect transistor T2 can be optionally connected to a substrate bias or to the ground V DD /V ss .
  • That part of the CMOS output stage critical to the invention is directed to the incorporation of the bypass transistor BT that forwards the positive over-voltages from the output OUT onto the supply voltage V DD .
  • the source, substrate and gate terminals of the p-channel bypass transistor BT are connected to the supply voltage V DD and the drain terminal is connected to the output OUT.
  • the bypass transistor BT inhibits during normal operation when no over-voltages appear.
  • positive over-voltages are adjacent at the output OUT, these being higher than the sum of the supply voltage V DD and the flow voltage of the bypass transistor, the bypass transistor BT becomes conductive and the positive over-voltage at the output OUT is dismantled.
  • the bypass transistor BT thereby sucks up additional charge carriers and thus boosts the trigger current in the parasitic bipolar transistors needed for the appearance of latch-up.
  • FIG. 2 shows a cross section relating to the CMOS output stage shown in FIG. 1.
  • An n-conductive, well-shaped semiconductor zone N w that extends up to the boundary surface PG is inserted within a semiconductor substrate P sub of doped semiconductor material, for example p-conductive silicon.
  • n + -doped semiconductor region N1, N2 that form the source and drain region of an n-channel field effect transistor T2 are inserted in the semiconductor substrate, whereas three p + -doped semiconductor regions P1, P2 and P3 that represent the source and drain regions of the p-channel field effect transistor T1 and of the p-channel bypass transistor PT are present within the well-shaped semiconductor zone N w .
  • the p + -doped semiconductor region P1 is used for the source terminal of the p-channel field effect transistor Pl and the p + -doped semiconductor region P3 is used for the source terminal of the p-channel bypass transistor BT; the p + -doped semiconductor region P2 forms the common drain terminal of the p-channel field effect transistor T1 and of the p-channel bypass transistor BT.
  • the p + -doped semiconductor region P1 is used for the source terminal of the p-channel field effect transistor Pl and the p + -doped semiconductor region P3 is used for the source terminal of the p-channel bypass transistor BT; the p + -doped semiconductor region P2 forms the common drain terminal of the p-channel field effect transistor T1 and of the p-channel bypass transistor BT.
  • the field effect transistors T1 and T2 are constructed as a CMOS output stage, whereby the n + -doped semiconductor region N1 is wired to the ground V ss as source terminal of the n-channel field effect transistor T2 and the n + -doped semiconductor region N2 forms the output OUT of the CMOS output stage and drain terminal of the n-channel field effect transistor T2.
  • the p + -doped semiconductor region P2 is likewise applied to the output OUT, whereas the p + -doped semiconductor region P1 is wired to the supply voltage V DD as source terminal of the same field effect transistor.
  • An input signal for the CMOS output stage is forwarded via the input IN to a first and second gate region G1 and G2 of the first or, respectively, second field effect transistor T1, T2, whereas an output signal can be taken at the output OUT.
  • the p + -doped semiconductor substrate P sub is connected to the ground or to a substrate bias V ss /V BB via an additionally p + -doped semiconductor region P4, whereas the n-conductive well-shaped semiconductor zone N w is wired to the supply voltage V DD via an n + -doped semiconductor region N3.
  • That part of the CMOS output stage critical to the invention is represented by the incorporation of the p-channel bypass transistor BT between the output OUT and the supply voltage V DD .
  • the drain terminal of the bypass transistor that is formed by the p + -doped semiconductor region P2 is wired to the output OUT and the source terminal realized by the p + -doped semiconductor region P3 and the gate terminal GB are wired in common to the supply voltage V DD .
  • the bypass transistor BT can be realized in a relatively simple way with an additional p + -diffusion for the p + -doped semiconductor region P3 and by an additional MOS gate GB.
  • the drain terminal of the bypass transistor BT represents the p + -doped semiconductor region P2 that is likewise utilized as drain terminal for the p-channel field effect transistor T1.
  • the risk of a latch-up effect in FIG. 2 is always established by the pnpn structure between the n + -conductive semiconductor region N1, the p-doped semiconductor substrate P sub , the n-conductive, well-shaped semiconductor zone N w and the p + -doped semiconductor region P2 whenever one of the pn-junctions is polarized in conducting direction.
  • the pnpn structure that is similar to a four-layer diode can be ignited as in the case of a thyristor. Such a high current then flows via the pn-junctions that either the junctions or the leads fuse, this potentially leading to a destruction of the CMOS output stage.
  • bypass transistor BT Due to the incorporation of the additional p-channel bypass transistor BT, positive over-voltage that appears at the output OUT and are adjacent at the p + -doped semiconductor region P2 is always carried off to the supply voltage V DD via the p-channel bypass transistor BT whenever the size of the over-voltage exceeds the sum of the supply voltage V DD and the conducting-state voltage of the bypass transistor. As already mentioned in FIG. 1, the bypass transistor BT suctions off the additional charge carriers and thus increases the trigger current needed for the appearance of latch-up effects. What is thereby important is that the bypass transistor BT has a conducting-state voltage that is lower than the conducting-state voltage of the pn-junctions of the p-channel field effect transistor T1.
  • the bypass transistor BT is particularly suited for reducing the latch-up risk when the n-conductive, well-shaped semiconductor zone N w of a p-channel MOS transistor wired as load element or as diode does not lie at a first potential, for example at the supply voltage V DD , but at variable potential for circuit-oriented reasons.
  • FIG. 3 shows an equivalent circuit diagram of a MOS transistor T1 wired in this way.
  • a p-channel bypass transistor BT is connected parallel in FIG. 3 to the p-channel field effect transistor T1 wired between the posts A and B.
  • a first terminal as well as the substrate terminal of the p-channel field effect transistor T1 and the gate region and a first terminal of the p-channel bypass transistor BT as well as the substrate terminal thereof are connected to the post A and a second terminal and the gate terminal of the p-channel field effect transistor T1 and a second terminal of the bypass transistor BT are connected to the post B.
  • the post A lies at a positive potential and the post B lies at a negative potential.
  • a parasitic, vertical bipolar transistor can thereby not be activated and lead to a latch-up.
  • the appearance of latch-up is always unavoidable when the post B has a potential that is greater than the sum of the potential at the post A and the conducting-state voltage of the pn-junction of the p-channel field effect transistor T1 (approximately 0.7 volts). Due to the additional incorporation of the bypass transistor BT, this becomes conductive when the voltage at the post B becomes greater than the sum of the conducting-state voltage of the bypass transistor and the voltage at the post A. In this case, the post A is connected to the post B in low-impedance fashion. The triggering of latch-up due to an activation of a vertical parasitic bipolar transistor is thus made more difficult.
  • FIG. 4 shows a realization of the equivalent circuit diagram recited in FIG. 3.
  • the n-conductive, well-shaped semiconductor zone N w that is embedded within the p + -doped semiconductor zone P sub is not connected to a fixed potential but to a variable potential at the post A via the n + -doped semiconductor region N4.
  • the conductive, well-shaped semiconductor zone N w extends up to the boundary surface PG and contains the p-channel field effect transistor T1 as well as the p-channel bypass transistor BT connected parallel thereto.
  • the p-channel field effect transistor T1 is constructed of the two p + -doped semiconductor regions P1 and P2 as well as of the gate region G1, whereby the p + -doped semiconductor region P1 that represents a first terminal of the p-channel field effect transistor T1 is connected to the post A and the p + -doped semiconductor region P2 that represents the second terminal of the p-channel field effect transistor T1 is connected to the gate region G1 at the post B.
  • the bypass transistor connected parallel is realized with the assistance of the p + -doped semiconductor region P2 and P3 as well as with the gate region GB, whereby the p + -doped semiconductor region P3 represents the first terminal of the bypass transistor and is connected to the gate region GB and to the post A and the p + -doped semiconductor region P2 represents the second terminal of the bypass transistor.
  • the p + -doped semiconductor region P2 thus fulfills a double function. First, it represents the second terminal of the p-channel field effect transistor T1 and, second, it forms the second terminal of the p-channel bypass transistor BT.
  • FIG. 5 A realization with a layout of a p-channel MOS transistor T1 wired as diode or load element having a bypass transistor BT based on the circuit recited in FIGS. 3 and 4 is shown in FIG. 5 as a view from above.
  • the gate regions G1 and GB as well as the p + -doped semiconductor regions P2 and P3 are arranged U-shaped around the p + -doped semiconductor region P1.
  • the reference characters selected in FIG. 3 and in FIG. 4 are likewise employed in FIG. 5 in order to show where the details of the p-channel MOS transistor T1 and of the p-channel bypass transistor BT of FIG. 3 and of FIG. 4 are arranged in the layout of FIG. 5.
  • the p + -doped semiconductor region P1 Recognizable from the plan view of FIG. 5 are the p + -doped semiconductor region P1, the gate region G1 and the p + -doped semiconductor region P2 that form the p-channel MOS transistor T1, whereby the p + -doped semiconductor region P2 in common with the gate region GB and the p + -doped semiconductor region P3 as well represent the p-channel bypass transistor BT.
  • the p + -doped semiconductor region P1 that is employed as first terminal of the p-channel field effect transistor T1 is constructed stripe-shaped and is connected to the post A.
  • the gate region G1 belonging to the p-channel field effect transistor T1 as well as the second terminal of the field effect transistor T1 that is illustrated by the p + -doped semiconductor region P2 are respectively arranged U-shaped around the p + -doped semiconductor region P1.
  • the second terminal of the p-channel field effect transistor T1 is thereby connected to the post B and is connected to the gate region G1 via an electrical connection B2.
  • the U-shaped arrangement of the gate region G1 and of the p + -doped semiconductor region P2 is fashioned such that the gate region G1 is first arranged around the p + -doped semiconductor region P1 and the p + -doped semiconductor region P2 lies around the gate region G1, whereby the gate region G1 is arranged above an imaginary plane erected through the p + -doped semiconductor regions P1, P2 and P3 and is separated from the p + -doped semiconductor region P1 and P2 by a thin insulating layer.
  • the gate region GB is constructed around the p + -doped semiconductor region P2 that is used as second terminal for the p-channel field effect transistor T1 and for the p-channel bypass transistor BT and the p + -doped semiconductor region P3 is constructed around the gate region GB.
  • polysilicon can be employed as gate material for both gate regions G1 and GB.
  • the p + -doped semiconductor region P3 which also represents the first terminal of the p-channel bypass transistor BT is connected to the gate region GB of the p-channel bypass transistor BT via a further electrical connection B3.
  • the gate region GB is again arranged over an imaginary plane erected through the p + -doped semiconductor regions Pl, P2 and P3 and is separated from the p + -doped semiconductor regions P2 and P3 by a thin insulating layer.
  • the illustration of FIG. 5 also shows that the n + -doped semiconductor region N4 is arranged stripe-shaped around the p + -doped semiconductor region P3 at a freely selectable distance L therefrom and is connected to the post A via an electrical connection B1.
  • the n + -doped semiconductor region N4 represents an electrical contact to the n-doped, well-shaped semiconductor zone N w that is shown in FIG. 5 with broken lines outside the n + -doped semiconductor zone N4.
  • the invention also covers embodiments wherein an n-conductive substrate is provided with p-conductive, well-shaped semiconductor zones.
  • the conductivity types of all semiconductor parts and the polarizations of all voltages are thereby replaced by their respective opposites.

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US07/477,929 1987-12-23 1988-10-24 Integrated circuit with anti latch-up circuit in complementary MOS circuit technology Expired - Lifetime US5041894A (en)

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DE3743930 1987-12-23
DE19873743930 DE3743930A1 (de) 1987-12-23 1987-12-23 Integrierte schaltung mit "latch-up"-schutzschaltung in komplementaerer mos-schaltungstechnik

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EP (1) EP0396553B1 (de)
JP (1) JP3174043B2 (de)
KR (1) KR0133204B1 (de)
AT (1) ATE106609T1 (de)
DE (2) DE3743930A1 (de)
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US5338986A (en) * 1992-05-28 1994-08-16 Oki Electric Industry Co., Ltd. Latch-up resistant CMOS output circuit
US5546020A (en) * 1994-04-18 1996-08-13 Hyundai Electronics Industries Co., Ltd. Data output buffer with latch up prevention
US5612643A (en) * 1994-03-30 1997-03-18 Nec Corporation Semiconductor integrated circuit which prevents malfunctions caused by noise
US5768078A (en) * 1995-11-13 1998-06-16 Hyundai Electronics Industries Co., Ltd. Electrostatic discharge protection circuit
US5990523A (en) * 1999-05-06 1999-11-23 United Integrated Circuits Corp. Circuit structure which avoids latchup effect
US6414360B1 (en) 1998-06-09 2002-07-02 Aeroflex Utmc Microelectronic Systems, Inc. Method of programmability and an architecture for cold sparing of CMOS arrays
CN101986428A (zh) * 2009-07-28 2011-03-16 英飞凌科技股份有限公司 功率半导体部件、包括其的功率半导体组件及其操作方法
CN108141181A (zh) * 2015-07-30 2018-06-08 电路种子有限责任公司 多级式且前馈补偿的互补电流场效应晶体管放大器
US20180219519A1 (en) 2015-07-30 2018-08-02 Circuit Seed, Llc Low noise trans-impedance amplifiers based on complementary current field-effect transistor devices
US10446547B2 (en) 2015-12-14 2019-10-15 Circuit Seed, Llc Super-saturation current field effect transistor and trans-impedance MOS device
US10514716B2 (en) 2015-07-30 2019-12-24 Circuit Seed, Llc Reference generator and current source transistor based on complementary current field-effect transistor devices
US10840854B2 (en) 2015-07-29 2020-11-17 Circuit Seed, Llc Complementary current field-effect transistor devices and amplifiers

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US5055903A (en) * 1989-06-22 1991-10-08 Siemens Aktiengesellschaft Circuit for reducing the latch-up sensitivity of a cmos circuit
DE19624474C2 (de) * 1996-06-19 1998-04-23 Sgs Thomson Microelectronics Monolithisch integrierte Mehrfachbetriebsartenschaltung
KR100726092B1 (ko) * 2006-08-31 2007-06-08 동부일렉트로닉스 주식회사 반도체소자 및 그 제조방법

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US5338986A (en) * 1992-05-28 1994-08-16 Oki Electric Industry Co., Ltd. Latch-up resistant CMOS output circuit
US5612643A (en) * 1994-03-30 1997-03-18 Nec Corporation Semiconductor integrated circuit which prevents malfunctions caused by noise
US5546020A (en) * 1994-04-18 1996-08-13 Hyundai Electronics Industries Co., Ltd. Data output buffer with latch up prevention
US5768078A (en) * 1995-11-13 1998-06-16 Hyundai Electronics Industries Co., Ltd. Electrostatic discharge protection circuit
US6414360B1 (en) 1998-06-09 2002-07-02 Aeroflex Utmc Microelectronic Systems, Inc. Method of programmability and an architecture for cold sparing of CMOS arrays
US5990523A (en) * 1999-05-06 1999-11-23 United Integrated Circuits Corp. Circuit structure which avoids latchup effect
CN101986428A (zh) * 2009-07-28 2011-03-16 英飞凌科技股份有限公司 功率半导体部件、包括其的功率半导体组件及其操作方法
CN101986428B (zh) * 2009-07-28 2013-01-23 英飞凌科技股份有限公司 功率半导体部件、包括其的功率半导体组件及其操作方法
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EP0396553B1 (de) 1994-06-01
HK59596A (en) 1996-04-12
WO1989006048A1 (fr) 1989-06-29
ATE106609T1 (de) 1994-06-15
DE3889921D1 (de) 1994-07-07
JP3174043B2 (ja) 2001-06-11
DE3743930A1 (de) 1989-07-06
EP0396553A1 (de) 1990-11-14
KR0133204B1 (ko) 1998-04-16
KR900701045A (ko) 1990-08-17
JPH03501669A (ja) 1991-04-11

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