US5343430A - Method and circuitry for screening a dynamic memory device for defective circuits - Google Patents

Method and circuitry for screening a dynamic memory device for defective circuits Download PDF

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US5343430A
US5343430A US07/695,014 US69501491A US5343430A US 5343430 A US5343430 A US 5343430A US 69501491 A US69501491 A US 69501491A US 5343430 A US5343430 A US 5343430A
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screening
mode
signal
refresh
terminal
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Tohru Furuyama
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Toshiba Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices

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  • the present invention relates to a semiconductor memory device and, more particularly, to a dynamic random access memory (DRAM) and a method for screening the same.
  • DRAM dynamic random access memory
  • a screening process is generally performed to expose latent defects in semiconductor devices and remove from finished batches those devices having defects. This screening process prevents defect-free devices from being adversely affected by defective devices and ensures the reliability of the finished semiconductor devices before and after they are put on the market.
  • semiconductor devices are operated using a voltage higher than the actual working voltage, and voltage stress is applied to the semiconductor devices for a period of time longer than the initial failure period under actual working conditions. The semiconductor devices are then screened and those which are considered likely to malfunction in initial operation are removed. This type of screening is an efficient method of removing defective devices, thereby enhancing the reliability of finished semiconductor devices.
  • the inventors of the present invention have proposed a semiconductor memory device wherein voltage stress can be applied simultaneously to all of the word lines, or to a larger number of the word lines than that selected in a normal operation mode.
  • This semiconductor memory device is disclosed in U.S. patent application Ser. No. 544,614 filed Jun. 27, 1990.
  • the semiconductor memory device proposed by the inventors greatly improves the efficiency of screening tests of transfer gates of memory cells.
  • the semiconductor memory device is in the form of a wafer
  • memory chip regions of the wafer can be screened in a short period of time by means of a prober and a probe card and, in this case, a number of probe terminals (for example, needles of the probe card) are not needed.
  • probe terminals are brought into contact with address signal pads on DRAM chip regions on a wafer to scan the address signals supplied from outside of the DRAM and access the word lines of the DRAMs in sequence. From the point of view of screening efficiency, it is desirable that the probe terminals be simultaneously placed in contact with the address signal pads of as many DRAM chip regions on the wafer as possible (ideally, the pads on all the DRAM chip regions).
  • a large number of probe terminals are required, it is difficult to attain such a probe card, and an address signal generator must be provided alongside the prober.
  • a dynamic memory device comprising a refresh counter, a row circuit, and a column circuit, the dynamic memory device having a screening refresh mode for activating a circuit block including the refresh counter, the row circuit, and the column circuit, in response to a signal other than a refresh address signal externally supplied.
  • a method for screening a dynamic memory device having a CBR (CAS Before RAS Refresh) mode and/or an ROR (RAS Only Refresh) mode wherein the CBR or ROR mode is designated by a signal supplied from outside of the DRAM (CAS is a column address strobe and RAS is a row address strobe).
  • CBR CAS Before RAS Refresh
  • ROR RAS Only Refresh
  • FIG. 1 is a block diagram schematically showing a DRAM according to the first embodiment of the present invention
  • FIG. 2 is a block diagram minutely showing the DRAM shown in FIG. 1;
  • FIGS. 3A and 3B are views of timing waveforms representing operations of different examples of a screening refresh mode setting circuit of the DRAM shown in FIG. 1;
  • FIG. 4 is a logic circuit diagram showing a modification to a refresh counter of the DRAM shown in FIG. 1;
  • FIG. 5 is a block diagram schematically showing a DRAM according to the second embodiment of the present invention.
  • FIG. 6 is a logic circuit diagram showing a refresh counter and an input data generator of the DRAM shown in FIG. 5;
  • FIG. 7 is a circuit diagram showing a circuit for generating screening signals SCR in the DRAMs shown in FIGS. 1 and 5;
  • FIG. 8 is a block diagram schematically showing a DRAM according to another embodiment of the present invention which is to be screened.
  • FIG. 9 is a block diagram minutely showing the DRAM shown in FIG. 8.
  • FIG. 1 is a block diagram schematically showing a DRAM according to the first embodiment of the present invention.
  • the DRAM shown in FIG. 1 has a CBR (CAS Before RAS Refresh) mode and/or an ROR (RAS Only Refresh) mode in order to facilitate a refresh operation, like a standard DRAM.
  • the DRAM also has a screening refresh mode described later.
  • reference numeral 1 indicates a power source terminal at a high potential; V CC , a power source potential; 2, a power source terminal (ground terminal) at a low potential; V SS , a ground potential; 3, a row address strobe (RAS) terminal for receiving an RAS signal; 4, a column address strobe (CAS) terminal for receiving a CAS signal; 5, a write enable (WE) terminal for receiving a WE signal; 6, a data input terminal; D in , data input; 7, a data output terminal; D out , data output; 11, a clock generator; 12, a refresh counter; 13, a row address buffer for receiving a row address signal or an output signal of the refresh counter 12; 14, a row circuit (e.g., a word drive circuit); A0 to A10, address signals; 15, a circuit block including a group of circuits activated by designating the CBR mode; 16, a column circuit (e.g., a circuit for reading data out of a sense amplifier); 17, a column address buffer for
  • a terminal 8 is supplied with a screening signal SCR for switching between a normal operation and a screening operation, and the screening signal SCR is input to a screening refresh mode setting circuit 9.
  • the circuit 9 sets an operation mode (corresponding to the screening refresh mode) for activating a circuit block 10, in response to a signal other than a refresh address signal supplied from outside of the DRAM.
  • the circuit block 10 includes the clock generator 11, refresh counter 12, row address buffer 13, row circuit 14, column circuit 16, and column address buffer 17.
  • FIG. 2 is a block diagram minutely showing the DRAM of the first embodiment having a 4M ⁇ 1 bit structure.
  • reference numeral 21 denotes a row decoder; 22, a memory cell array; 23, a sense amplifier; 24, a column decoder; 25, an I/O gate; 261, a data input buffer; 262, an intermediate input buffer; 271, a data output buffer; 272, an intermediate output buffer; 28, a control signal input buffer; 291, a first clock signal generator; 292, a second clock signal generator; 30, a refresh controller; and 31, a substrate bias generator.
  • the clock signal generators 291 and 292 constitute the clock generator 11.
  • the row decoder 21, memory cell array 22, and sense amplifier 23 are included in the row circuit 14.
  • the column decoder 24, I/O gate 25, intermediate input buffer 262, intermediate output buffer 272 are included in the column circuit 16.
  • the data input buffer 261 and data output buffer 271 constitute the I/O circuit 18.
  • a logic circuit of screening refresh mode setting circuit 9 is so constructed as to detect that the CBR mode is designated when the screening signal SCR is input (when an activation level is low), as is apparent from the timing waveform shown in FIG. 3A. Then the circuit block 10 is activated by a detection output of the logic circuit.
  • a logic circuit is so constructed as to detect that the ROR mode is designated when the screening signal SCR is input (when the activation level is low), as is apparent from the timing waveform in FIG. 3B. Then the logic block 10 is activated by a detection output of the logic circuit.
  • the number of external terminals required for setting the screening refresh mode is decreased by one corresponding to the CAS terminal 4.
  • a high resistance be connected between the CAS terminal 4 and power source potential V CC and the input CAS signal is pulled up to a high level.
  • an output signal of the refresh counter 12 is input in common to the row address buffer 13 and column address buffer 17 in order to uniformly apply a stress to the row circuit 14 and column circuit 16. Furthermore, the screening refresh mode disables the output buffer 271 of the I/O circuit 18 from operating, as in the ROR mode in the normal operation.
  • the CBR mode is designated by activating the CAS signal first and then the RAS signal. If the CBR mode is designated in the normal operation, the circuit block 15 including the refresh counter 12 and row circuit 14 is operated, and a refresh address signal is supplied from the refresh counter 12 to the row address buffer 13, thereby refreshing memory cells (not shown) of the memory cell array 22.
  • the ROR mode is designated by not activating the CAS signal, but rather activating the RAS signal only. If the ROR mode is designated in the normal operation, the circuit block 19, which includes not only the row circuit 14 but also the column circuit 16 minus output buffer 271, is operated, but the refresh counter 12 is not operated. If a refresh address signal is supplied from outside of the DRAM in this state, the memory cells are refreshed.
  • the screening refresh mode is set only by supplying a signal other than the refresh address signal from outside the chip regions, the word lines (not shown) of the memory cell array 22 are accessed in sequence without receiving any refresh address signal from outside the chip regions, and a stress is applied to the transfer gates of the memory cells to the utmost; accordingly, the screening can be performed.
  • the required input terminals on the DRAM chip regions, or the signals input from the terminals are reduced in number, and no address signal generator needs to be provided at the side of a screening apparatus.
  • the probe terminals required per chip on the wafer is decreased in number. Therefore, the probe card can be easily made, the screening can be easily performed, and no address signal generator needs to be provided at a side of the prober.
  • FIG. 4 is a logic circuit diagram showing a modification to the refresh counter 12.
  • the refresh counter shown in FIG. 4 includes a row refresh counter RRC and a column refresh counter CRC and is so constructed that an output of the column refresh counter CRC is carried by one if the row refresh counter RRC produces a round of outputs. More specifically, set/reset type flip-flops 1201 to 1218 are connected in series so that outputs signals Q and Qof the preceding flip-flop, which are complementary to each other, are supplied as input signals of the succeeding flip-flop, and the flip-flops constitute a frequency dividing circuit.
  • the flip-flop 1201 at the first stage is supplied with clock signals CK, CKcomplementary to each other which are generated from the clock generator 11 when the screening refresh mode is set.
  • the flip-flops 1201 to 1218 at their respective stages divide the frequencies of their input signals in half.
  • the flip-flops at the first to ninth stages constitute the row refresh counter RRC, and a 9-bit output signal of the row refresh counter RRC is supplied to the row address buffer 13 through a multiplexer (not shown).
  • the flip-flops 1210 to 1218 at the tenth to eighteenth stages constitute the column refresh counter CRC, and a 9-bit output signal of the column refresh counter CRC is supplied to the column address buffer 17 through the multiplexer (not shown).
  • the output signal of the column refresh counter CRC is used only when the screening is performed.
  • the data output buffer 271 Of the I/O circuit 18 is not caused to operate in the screening refresh mode.
  • the buffer 271 can be however operated in this mode. If data output terminal 7 is rendered in a floating state in view of potential, an increase in current due to data output is a small matter. It is thus possible to apply a dynamic stress to the data output buffer 271 of the I/O circuit 18.
  • the sense amplifier 23 of the row circuit 14 operates so that a selected one of a paired bit lines (not shown) of the memory cell array 22, which are complementary to each other, the selected bit line being at the memory cell side, is always at a low level.
  • Each of the bit lines is set at a low level at the same ratio and therefore the dynamic stress is uniformly applied to the sense amplifying system. If the data output buffer 271 is operated, "0" and "1" are output at the same ratio and the dynamic stress is uniformly applied.
  • the DRAM thus allows an expected stress to be applied, without using an input data generator.
  • the input data can be supplied from outside of the chips. It is more desirable to decrease the number of external terminals for screening, as in a DRAM shown in FIG. 5.
  • FIG. 5 is a block diagram schematically showing the DRAM according to the second embodiment of the present invention.
  • the DRAM shown in FIG. 5 differs from that in FIG. 1 only in the use of an algorithm wherein an input data generator 50 is formed on a chip and supplied with a clock signal from the clock generator 11, the write and read operations are changed to each other after a round of refresh address signals is generated, and the input data is changed to another after a round of write and read operations is completed.
  • a circuit satisfying this algorithm is proposed by the inventors of the present invention in Published Unexamined Japanese Patent Application Nos. 63-66798 and 63-66799 to Furuyama et al. Such a circuit is shown in FIG. 6.
  • the functions of both the input data generator 50 and refresh counter 12 can be performed by the circuit shown in FIG. 6.
  • set/reset type flip-flops 5001 to 5020 are connected in series so that outputs signals Q and Qof the preceding flip-flop, which are complementary to each other, are supplied as input signals of the succeeding flip-flop.
  • the flip-flop 5001 at the first stage is supplied with clock signals CK and CKcomplementary to each other which are generated from the clock generator 11 when the screening refresh mode is set.
  • the flip-flops 5001 to 5020 at their respective stages divide the frequencies of their input signals in half.
  • the flip-flops 5001 to 5009 at the first to ninth stages constitute the row refresh counter RRC, and the flip-flops 5010 to 5018 at the tenth to eighteenth stages constitute the column refresh counter CRC.
  • the output signals W/R and W/R of the flip-flop 5019 at the ninth stage are used as a write/read signal for setting a data write mode and a data read mode.
  • the flip-flop 5020 at the twentieth stage corresponds to the input data generator 50, and their output signals D and Dcomplementary to each other are supplied through a data multiplexer (not shown) and used as write data.
  • Q output signals (a0R to a8R, a0C to a8C, W/R, D) of all the flip-flops 5001 to 50020 are set to "0" level, and Qoutput signals (a0Rto a8R, a0Cto a8C, W/R, D) are set to "1" level by initialization.
  • the write/read signal W/R thus becomes “0" level, the data write mode is set, and the write data becomes "0".
  • the screening refresh mode is thus selected and the clock signals CK and CKare input from the clock generator 11, row address signals a0R to a8R and a0Rto a8R, and column address signals a0C to a8C and a0Cto a8Care changed in sequence, and data of "0" level is written in the memory cells of the memory cell array 22. If a round of the row and column address signals is generated, the write/read signal W/R is set at "1" level, and the data read mode is selected. If a round of the row and column address signals is generated again, the write/read signal W/R is set at "0" level, and output data D of the flip-flop 5020 changes from “0" to "1".
  • the data write mode is selected again, and the write data becomes "1". If the row and column address signals are then changed, data of "1" level is written in the memory cells of the memory cell array 22. Further, if a round of the row and column address signals is generated, the write/read signal W/R is set at "1" level, and the data read mode is selected.
  • the screening signal SCR is input from outside of the DRAM through the terminal (pad) 8 on a DRAM chip which is in the form of a wafer, or the screening signal SCR is input from outside of the DRAM through the terminal 8 after a DRAM chip is separated from another chips by division of the wafer and then packaged.
  • the number of external terminals necessary for setting the screening refresh mode is five, that is, power source terminal 1, ground terminal 2, RAS terminal 3, CAS terminal 4, and terminal 8.
  • the screening signal SCR is generated on a DRAM chip on the basis of an address key code which is input as an option of a WCBR (WE and CAS before RAS) mode standardized by the Joint Electron Devices Engineering Council (JEDEC) with respect to the 4-bit DRAM, or a mode which changes to a test mode if the WE and CAS signals are activated when the RAS signal is activated.
  • the number of external terminals necessary for setting the screening refresh mode is six, that is, a terminal for inputting the address key code in addition to power source terminal 1, ground terminal 2, RAS terminal 3, CAS terminal 4, and terminal 8.
  • the external terminals necessary for setting the screening refresh mode correspond to plural terminals which receive the signal representing the above order, in addition to power source terminal 1 and ground terminal 2.
  • the number of external terminals necessary for setting the screening refresh mode is three, that is, power source terminal 1, ground terminal 2, and terminal receiving the above signal.
  • FIG. 7 is a circuit diagram which shows, as an example of the fourth means described above, a ternary control circuit for detecting that a voltage higher than a predetermined voltage is applied to an address terminal 71 of the uppermost bit.
  • Two P-channel MOS transistors P1 and P2 and one N-channel MOS transistor N1 are connected in series between the address terminal 71 and ground potential V SS .
  • the gate and drain of the transistor P1 are connected to each other, and power source potential V CC is applied to the gates of the transistors P2 and N1.
  • An inverter IV is connected to a series-connecting point of the transistors P2 and N1.
  • the transistor P1 when a normal potential at a high level (corresponding to V CC ) or at a low level (corresponding to V SS ) is applied to the address terminal 71, the transistor P1 is turned off and a potential of the input node of the inverter circuit IV is set to be low by the transistor N1 in its ON-state. For this reason, the screening signal SCR output from the inverter Iv becomes high in level (inactive state).
  • a control voltage (V CC +2vthp or more; vthp is a threshold voltage of the P-channel MOS transistor P1), which is higher than V CC , is applied to the address terminal 71, the transistor P1 is turned on, the potential of the input node of the inverter IV exceeds V CC , and the screening signal SCR output from the inverter IV becomes low in level (active state).
  • the screening can be performed by accessing the word lines of a memory in sequence and applying a stress to almost all the transfer gates of the memory.
  • the number of input terminals of the DRAM, or the number of signals input from the input terminals, required for setting the refresh mode for screening is decreased, and an address signal generator need not be provided at the side of a screening apparatus.
  • the number of probe terminals required per chip on the wafer is reduced. A probe card is thus easy to be prepared, the screening is also easy to be performed using a probe, and an address signal generator is not needed at the prober side.
  • FIG. 8 is a block diagram schematically showing a DRAM according to another embodiment of the present invention which is to be screened.
  • FIG. 9 is a block diagram minutely showing the DRAM shown in FIG. 8 having a 4M ⁇ 1 bit structure.
  • the DRAM shown in FIGS. 8 and 9 has a CBR mode and/or a ROR mode as a standard DRAM, it does not have the foregoing refresh mode for screening, nor does the refresh counter 12 supply a refresh address signal to the column address buffer 17.
  • the DRAM shown in FIG. 8 When the DRAM shown in FIG. 8 is packaged or shaped like a wafer, it can be set into the CBR mode by applying signals necessary for designating the CBR mode from outside (applying the CAS signal first, and then the RAS signal). The circuit block 15 is thus activated, and a refresh address signal is supplied to the row address buffer 13. A dynamic stress can thus be applied to the activated circuit block 15.
  • the screening method described above is made effective if the row circuit 14 is intensively and sufficiently screened.
  • the row circuit 14 is operated by designating the CBR mode, but the column circuit 16 is not operated; accordingly, only the static stress is applied to the column circuit 16 to which the dynamic stress has been applied in normal operating condition.
  • it is indefinite what initial value is set to the memory cell. The initial value may be set so that the sense amplifier shown in FIG. 9 operates only in a direction of an output having a constant logic level, and a stress cannot be uniformly applied to a sense amplifying system.
  • the second embodiment of the screening method four external terminals are necessary for setting the CBR mode, namely power source terminal 1, ground terminal 2, RAS terminal 3, and CAS terminal 4.
  • a DRAM having a 4M ⁇ 1 bit structure requires eighteen address terminals.
  • the number of terminals necessary for setting the CBR mode in the second embodiment of the screening method is about one fourth of that of terminals in the conventional screening method wherein an address signal is supplied from outside. Consequently, the number of input terminals of the DRAM (or the number of signals input to the DRAM) required for the screening is very small, and an address signal generator need not be provided at the screening apparatus side.
  • probe terminals required per chip on the wafer is decreased in number.
  • a probe card is thus easy to be prepared, a screening is easy to be performed, and an address signal generator need not be provided at the prober side.
  • the DRAM shown in FIG. 8 When the DRAM shown in FIG. 8 is packaged or shaped like a wafer, the DRAM is set in the ROR mode by supplying an RAS signal from outside of the DRAM.
  • the circuit block 19 including not only the row circuit 14 but also the column circuit 16 excluding the data output buffer 271, is operated. Though the refresh counter 12 is not then operated, if a row address signal is supplied from outside of the DRAM, a stress can be applied to both the row and column circuits 14 and 16.
  • the screening method described above is effective if the column circuit 16 is intensively and practically screened and, in other words, is effective when a stress test for the sense amplifier 23 or a transfer circuit for transferring data from the sense amplifier 23 is carried out after a stress test for the word lines of the memory cell array 22 shown in FIG. 9 is finished.
  • the number of input terminals of the DRAM (the number of signals input to the DRAM) necessary for the screening is smaller than that in the conventional screening method.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
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JP2119949A JPH0821607B2 (ja) 1990-05-11 1990-05-11 ダイナミック記憶装置およびそのバーンイン方法

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US5448742A (en) * 1992-05-18 1995-09-05 Opti, Inc. Method and apparatus for local memory and system bus refreshing with single-port memory controller and rotating arbitration priority
US5475646A (en) * 1992-08-31 1995-12-12 Kabushiki Kaisha Toshiba Screening circuitry for a dynamic random access memory
US5495452A (en) * 1993-07-14 1996-02-27 Samsung Electronics Co., Ltd. Circuit for controlling a self-refresh period in a semiconductor memory device
US5515331A (en) * 1994-03-12 1996-05-07 Gold Star Electron Co., Ltd. DRAM refresh control circuit
US5517454A (en) * 1993-12-27 1996-05-14 Kabushiki Kaisha Toshiba Semiconductor memory device having refresh circuits
US5881011A (en) * 1997-06-28 1999-03-09 Hyundai Electronics Industries Co., Ltd. Memory device for performing a refresh operation under an active mode
US5959925A (en) * 1998-06-01 1999-09-28 Mitsubishi Denki Kabushiki Kaisha DRAM incorporating self refresh control circuit and system LSI including the DRAM
US20030169634A1 (en) * 2002-03-11 2003-09-11 International Business Machines Corporation Memory array system
US20090287362A1 (en) * 2007-02-01 2009-11-19 Fujitsu Limited Monitored burn-in test apparatus and monitored burn-in test method
US9082504B2 (en) 2012-07-12 2015-07-14 Samsung Electronics Co., Ltd. Semiconductor memory device storing refresh period information and operating method thereof

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US9082504B2 (en) 2012-07-12 2015-07-14 Samsung Electronics Co., Ltd. Semiconductor memory device storing refresh period information and operating method thereof

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KR940010665B1 (ko) 1994-10-24
EP0456255A3 (en) 1991-12-27
DE69128978D1 (de) 1998-04-09
JPH0417349A (ja) 1992-01-22
DE69128978T2 (de) 1998-07-16
JPH0821607B2 (ja) 1996-03-04
KR910020730A (ko) 1991-12-20
EP0456255B1 (de) 1998-03-04
EP0456255A2 (de) 1991-11-13

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