US5421010A - Circuit and a method for selecting the kappa greatest data in a data sequence - Google Patents

Circuit and a method for selecting the kappa greatest data in a data sequence Download PDF

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US5421010A
US5421010A US08/267,293 US26729394A US5421010A US 5421010 A US5421010 A US 5421010A US 26729394 A US26729394 A US 26729394A US 5421010 A US5421010 A US 5421010A
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data
bits
value
output
word
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Alain Artieri
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STMicroelectronics SA
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SGS Thomson Microelectronics SA
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/22—Arrangements for sorting or merging computer data on continuous record carriers, e.g. tape, drum, disc
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99931—Database or file accessing
    • Y10S707/99937—Sorting

Definitions

  • the present invention relates to circuits for sorting data according to a predetermined criterion and particularly to a circuit enabling to sort the k greatest data among sequentially incoming data.
  • Such sorting circuits are for example useful in the field of image compression systems. Indeed, in this field, it is desired to transmit as few data as possible representing an image in the best possible way. In particular, data are cancelled according to a predetermined criterion in order to increase the compression efficiency while decreasing the complexity and processing time which increase along with the number of non-null data.
  • images are divided into blocks, for example 8 ⁇ 8 pixels, associated with matrices, each coefficient of which represents the luminance and chrominance information of a pixel.
  • matrices are subject, for example, to a discrete cosine transform (DCT); then, one obtains transformed matrices of equal size, the advantage of which is to have many practically null coefficients.
  • DCT discrete cosine transform
  • a first technique of the prior art for providing the greatest coefficients of the transformed matrix consists of sequentially reading the coefficients and comparing them with a threshold value in order to cancel the coefficients that are smaller than the threshold.
  • the drawback of this technique is that all the coefficients of a matrix are cancelled if they are too small; this causes significant degradation of the restored image because the largest of such small coefficients carry a significant information.
  • Another drawback is that none of the coefficients are cancelled if they all are larger than the threshold; in this case the desired compression is not achieved.
  • Another approach consists of keeping only a predetermined number k of the largest data values. This prevents cancellation of small values, that are nevertheless representative of the image, and also ensures that no more than k data values will have to be processed during subsequent steps.
  • the known circuits for implementing this technique have had the drawback of being complex and relatively slow.
  • the disclosed inventions provides a simple method for implementing this other technique.
  • the preferred embodiment of the invention provides a method of sorting the k greatest data in a sequence of n data sequentially incoming in the form of binary logic signals, comprising the following steps: a) sequentially writing each datum in one of n memories each adapted to receive one word comprising in a decreasing weight order the following bits: a first inhibition bit, a second selection bit, third data bits, fourth bits corresponding to a number representative of the rank of the incoming datum; b) setting to "1" the first bits of the n words when the first signal of the data sequence occurs; c) while writing each datum, resetting the first and second bits of the corresponding word; d) between the arrivals of the signals corresponding to the (n-k) th datum and n th datum, detecting the smallest word stored in the memories and setting its second bit to "1"; and e) as soon as signals corresponding to the n th datum have arrived, sequentially reading the stored data and processing the data associated to a word having its second bit to
  • step e data are read according to the sequence they have been written during step a).
  • the invention further provides apparatus for sorting the k greatest data in a sequence of n data sequentially arriving on an input bus as binary logic signals, comprising: a memory point matrix of n columns and m rows, each column being assigned to a word corresponding to one of the data and comprising in the order of increasing row numbers and decreasing bit weights: a first inhibition memory point set to "1" by an initialization signal and reset by the incoming datum, a second selection memory point connected to an output bus line, reset by the incoming datum, third memory points connected to the lines of the data input bus and of a data output bus, for receiving and storing the datum, and fourth memory points containing a number representative of the incoming datum rank; a first circuit for addressing each of the columns according to the incoming rate of the data and storing therein the datum present on the lines of the input bus; a second circuit active only between the arrival of the (n-k) th datum and the n th datum for detecting the smallest word and setting its second memory point as soon
  • the second circuit is constituted by modules, each being associated with a memory point and comprising: a connection at the output Q of the associated memory point, an exclusion output X ij , which, if the arriving row i is the last one, is connected to a set input of the second memory point of the current column j, an intermediate output, an exclusion input connected, either to the exclusion output x i-1 ,j of the module of the current column j and of the preceding row i-j, or to a reset input if the current row is the first, a detection input connected to the output Zi of a logic detection means common to all modules of the current row j and receiving at the input the intermediate outputs of these modules; output X ij taking the values listed in the following table where symbol "#" indifferently designates 0 or 1:
  • the logic detection means provides the value 0 at its output Zi only when all the intermediate outputs of the modules of the current row; are set to "1".
  • the circuits for addressing each column comprise a shift register.
  • the second memory points are authorized to be set to "1" by an active enabling signal between arrivals of the (n-k) th datum and n th datum.
  • An advantage of the invention is that the selection of the k greatest data is achieved as soon as the last data of a sequence has arrived, while in the prior art it is necessary to sort out and order data in decreasing order in a memory, then, to sort out the k first ones.
  • FIGS. 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1J, 1K, 1L, 1M, 1N, 1O, and 1P represent one after the other the successive steps of the method according to the invention in a practical case;
  • FIG. 2 is a simplified modular diagram of one embodiment of the selection circuit according to the invention.
  • FIG. 3 is an electrical diagram illustrating one of the modules of FIG. 2;
  • FIG. 4 shows time diagrams characterizing the operative cycles of the circuits of FIGS. 2 and 3;
  • FIG. 5 represents a modification of one of the modules in relation to the circuit of FIG. 2 as used for avoiding possible drawbacks.
  • any element affected with index j corresponds to the j th datum of the sequence.
  • each datum Dj in binary mode is associated a word comprising additional bits, namely, in decreasing order of bit weight, an inhibition bit Ij, a selection bit Sj, data bits Dj, and priority bits Pj.
  • Bits Pj represent in binary mode a priority coefficient n-j (here 8-j).
  • Each of the words is stored in a memory, for example in a column.
  • the content of the memory is illustrated in a table shown in FIGS. 1A-1P at various filling steps, the first row representing the states of inhibition bits I, the second row the states of selection bits S, the third row the decimal values of data D and the fourth the decimal values of the priority coefficients P.
  • FIG. 1A shows the state of this table as soon as the first datum D1 of a sequence of 8 data occurs.
  • Symbol "#" represents a random value.
  • bits I of the 8 columns are set.
  • the first column is selected for writing (such column being designated with letter W on top of the column).
  • Datum D1 is written in the column and simultaneously bits I1 and S1 are reset.
  • the fifth datum Ds is written in the same way in the fifth column of the table.
  • the smallest word in the 8 columns is detected, the detection being represented by a framed column.
  • it is one of the words of the first 5 columns since their first inhibition bits I have been reset while the first inhibition bits I of the words of the other columns remain set.
  • it is the word of the first column; its selection bit S1 is set to "1" as soon as the next datum D6 incomes, as shown in FIG. 1F. Setting to "1" is indicated by a framed 1. Because the selection bit S1 of the word of the first column (the smallest) is set, it becomes the greatest among the five that have just been written and it will no longer be selected as the smallest during the subsequent comparisons.
  • Data D6-D8 are similarly written in columns 6-8 during the steps illustrated in FIGS. 1F-1H. One successively detects that the words of columns 6, 5 and 8 are the smallest and their selection bits S 6 , S 5 and S 8 are set.
  • FIG. 1H while datum D 8 is being written, the data reading sequence is started.
  • each datum is read in its arrival order with the corresponding selection bit S.
  • a column selected for reading is designated with letter R on its top.
  • selection bit S marks with a 0 the four greatest data and with 1 the others. Then, it is possible, for example as part of an application to image compression, to cancel the data marked with 1.
  • a drawback may result from the fact that the first datum D1 is the last datum marked by setting of with bit S1.
  • bit S1 the last datum marked by setting of with bit S1.
  • FIG. 1H datum D1 will be read with its selection bit S1 which has not yet been set a "1", since this bit will be set to "1" only the next time interval, as shown in FIG. 1I.
  • this situation never appears because the first data are the greatest, especially when the circuit processes data from a cosine transform.
  • a solution to this drawback is proposed in FIG. 5.
  • This method is easy to generalize for selecting the k greatest data in a sequence of n data.
  • n words and columns instead of 8
  • the selection of the (n-k) smallest of these n words is operative after the arrival of the (-k) th datum.
  • the selection becomes inactive the (n-k) smallest columns having been marked by setting their selection bits S to a "1".
  • the other k columns are marked with a O for their corresponding selection bits S; this indicates that the k largest data are written in these columns.
  • the n data are read together with their selection bits S, so that it is possible to cancel those having a "1" as their selection bits S.
  • FIG. 2 shows a specific embodiment of a circuit implementing the above described method.
  • the circuit comprises a matrix of modules for bit storing and processing.
  • the matrix comprises n columns, like those in the tables of Figs 1A and 1B.
  • the matrix comprises m rows, where m corresponds to the number of bits in a column of the above described tables.
  • the first row comprises MI modules (MI 11 . . . MI 1j . . . MI 1n ) for storing the inhibition bits I.
  • the second row comprises modules MS (MS 21 . . . MS 2j . . . MS 2n ) for storing the selection bits S.
  • the r next rows (r being the number of bits of a datum to be processed) comprise modules MD (MD 31 , . . . MD 3j . . . MD 3n to MD 2+r ,1 . . . MD 2+r ,j . . . MD 2+r ,n)
  • the p last rows comprise priority modules MP (MP 3+r ,1 . . . MP 3+r ,j . . . MP 3+r ,n to MP m1 . . . MP mj . . . MP mn ) for storing in binary mode the priority words designated by letter P in the tables of FIGS. 1A-1P (p represents the number of bits necessary for coding numbers 0 to n-1).
  • Each module comprises: an input bit input (except for modules MP), an output bit (except for modules MI and MP), an exclusion input, an exclusion output X ij , a read enable input (except for MP modules) and a write enable input (except for modules MP).
  • Modules MI and MS additionally comprise a SET input.
  • Modules MP code in binary mode priority coefficients in a fixed way.
  • the bit input is connected to a line INi of an input bus, the bit output being connected to a line OUTi of an output bus and the exclusion output X ij being connected to the exclusion input of the module of the next row i+1.
  • the write enable input is connected to a line W j of a write address bus and the read enable input is connected to a line R j of a read address bus.
  • the first read line R i is connected to the last write line W n , which causes reading of the first column and writing of the last, simultaneously.
  • Lines W and R are controlled by a conventional addressing circuit 11, constituted, for example, by a shift register, controlled by a clock CK and by an initialization signal INIT which is also applied to the first write line W 1 .
  • the bit inputs of the first two rows are connected to the logic level 0 (ground).
  • the exclusion inputs of modules MI are connected to the logic level O.
  • the exclusion output X mj of each module MP mj of the last row is connected to the input D of a flip-flop 10.
  • Each D-type flip-flop 10 comprises an inverted output Q* connected to the SET input of module MS of the corresponding column, an enabling input connected to a clock CK and a SET input connected to an enabling line VAL common to all flip-flops 10.
  • each column of the modules MI, MS, MD and MP there is a memory point adapted to store a bit of the word as contained in the corresponding column of the tables of FIGS. 1A-1P.
  • successive data are written in modules MD of successive columns.
  • the comparison operations are active for the k last written data.
  • Each module MI, MS, MD and MP comprises, in addition to the memory point, a logic processing unit which, in combination with the one of all the other modules, carries out the above explained operations, namely, comparing the values of the words stored in the columns for selecting a column. (This selection operation consists in fixing the selection bit S of the module MS of each column).
  • the modules are sequentially analyzed row after row, starting from the first row.
  • the modules in the first row are first considered.
  • the modules containing a "1" (as shown in column 8) will then correspond to the largest words, and each of these modules will provide for the lower module, through its exclusion output, an exclusion bit (shown above by an underlined number) which extends downwards from one module to the other so as to exclude the corresponding column from having a subsequent analyses.
  • an exclusion bit shown above by an underlined number
  • this circuit has to take into account some additional logic combinations, i.e., a no exclusion bit is authorized to be emitted in the case when, for all the columns not previously excluded, all the modules of the same row contain a "1" (for example, in TABLE I modules MD 42 , MD 43 and MD 45 , then modules MD 62 and MD 65 , then, module MP 85 and finally module MP 95 ).
  • FIG. 3 illustrates one of the modules in the form of a logic circuit.
  • a memory point is constituted by a D-type flip-flop 20 having a bit input D connected to one of the input lines IN i ; an enable input connected to one of the write lines W j ; an output Q connected to one of the output lines OUTd through a three-state gate 21 activated by a control input connected to one of the read lines Rj; and a SET input.
  • Modules MP do not include any flip-flop and the lines for MI and MP correspond to the flip-flop outputs. They are connected either to ground (logic 0), or to the supply voltage Vcc (logic 1) for establishing in binary mode the priority coefficients n-j.
  • An OR gate 22 receives the output Q of flip-flop 20 and the exclusion output x i-1 ,j of the module of the preceding line.
  • the output of the OR gate 22 feeds the gate of a P-channel MOS transistor 23, the source of which is connected to the supply voltage Vcc and the drain to line Zi
  • a resistive means 24 (one per line) connects line Zi to ground. All the MOS transistors 23 of the same row and the resistive means 24, constitute an NAND gate.
  • Such a NAND gate has an output line Zi and its inputs are each connected to the outputs of the OR gate 22 of the same row.
  • the OR gate can be considered as a zero detector which provides a "1" at its output when at least one of its inputs is at "0".
  • An AND gate 25 receives the output of the AND gate 25 and the exclusion output x i-j of the preceding module.
  • the output of OR gate 26 constitutes the exclusion output X ij .
  • a module operates as follows.
  • a "1" on its exclusion input (xi-1, j-1) indicates that the column is to be excluded from analyses, i.e., a bit "1" has been detected in at least one of the modules of the column for the preceding rows.
  • This "1" is present at one of the inputs of the OR gate 26 and is transmitted to its output, which is the exclusion output X ij .
  • this function for each module is to directly transmit an exclusion bit provided by a preceding module of the same column.
  • Line Zi is forced to 1 by any of the modules of the same row, the MOS transistor 23 of which is conductive, that is, the OR gate 22 of which has its output to 0. This occurs only if the exclusion input and the content of the flip-flop are both equal to 0, which means that the column to which belongs the considered module inevitably contains one of the smallest words.
  • Line Zi is forced to 0 by the resistive means 24 only if all the MOS transistors 23 of the modules of a same row are off. This occurs when each of the modules of the row has its exclusion input equal to 1 or the content of its flip-flop 20 to 1. This happens when all the modules of the row and in the non-excluded columns contain "1" in their flip-flop 20. In that case, all the outputs of the AND gates 25 of the modules of the row are to "0" and this 0 is transmitted to the exclusion outputs of all the modules of the row contained in the non-excluded columns.
  • the three columns respectively show: the values taken by line Z i , the exclusion output of the module of the preceding row i-1 and of the same column j, and the exclusion output X ij of the considered module.
  • Symbol "#" represents indifferently a 0 or a 1 and Q designates the content of flip-flop 20 for the considered module.
  • each module carries out the following "write” and “read” operations.
  • a "1" present on line Wj (which is connected to the enable input of flip-flop 20) charges into the flip-flop the bit present at that time on line INi which is connected to the bit input D of the flip-flop.
  • a "1" present on the read line Rj (which is connected to the control input of the three-state gate 21) transmits the content Q of the flip-flop onto the line OUTi which is connected to the output of the three-state gate 21.
  • FIG. 4 shows a time diagram wherein CK is the clock signal; INIT the initialization signal applied to line W 1 and at the input of the addressing circuit 11; VAL the enabling signal applied to the enable line; Din the times at which each datum Dj appears on the lines INi of the input bus; and Dout the times at which each datum Dj appears at the circuit output on lines OUTi of the output bus.
  • signal INIT is set to 0 while signal VAL is to "1".
  • Signals Din and Dout are random signals.
  • signal INIT is set to "1" during a clock period, while authorizing "writing” of datum D1 in modules MD of the first column; the flip-flops of modules MI of the first row are set to "1" and the addressing circuit 11 is initialized.
  • the addressing circuit During the next rising edge of the clock signal which corresponds to the occurrence of the next datum D2, the addressing circuit exhibits a "1" on line W2 during a clock period, thereby to authorize "writing" datum D2 into modules MD of the second column, and so forth until the n data have been written successively in each set of modules MD il -MD in .
  • all the matrix modules start calculating the column containing the smallest word and a 0 appears at the exclusion output of the last module of the column.
  • signal VAL is set to "0" until the n th datum is written.
  • flip-flops 10 are active, that is, their outputs Q* are no longer forced to 0 by signal VAL and so that they will take into account the bits present at their inputs.
  • flip-flop 10 of the column containing the smallest word transmits to its output Q a 1 which sets the corresponding module MS.
  • the addressing circuit 11 authorizes the first datum D1 to be transferred as well as the selection bit S1 distributed and stored in modules MD 31 -MD 2+rl and MS1 on the data output bus, and so forth until modules MD and MS of the last column are "read".
  • FIG. 5 illustrates a modification of the circuit according to the invention, intended for avoiding the above drawback, wherein, when the first datum D1 is the last datum marked, the marking bit S1 of datum D1 has not yet been forced to a 1 whereas the marking bit and datum D m are "read".
  • FIG. 5 partially shows the circuit including a modified module MS21, the last module MP ml and the flip-flop 10 as used for setting module MS21.
  • the marking bit S 1 present on line OUT2 is set a short time after the bits of datum D 1 is set on the other lines OUT.
  • this delay lower than the half clock period, will not cause any error.
  • a circuit known and easy to implement by those skilled in the art can be placed after the circuit of FIG. 2 in order to cancel any data marked by "1" appearing in their corresponding selection bits S.
  • circuit of the embodiment of the invention described in relation with FIG. 2 is of a systolic-array type circuit in which each module constitutes a systole. This type of circuit is easily integrable because of its simple routing.
  • Tz+(m-1)TM designates the setting time of a bit on a line Z
  • m designates the number of modules in a column
  • TM designates the time necessary for calculating a module. This period is particularly short.
  • the invention has been described as part of an image processing, but it applies to any case where it is desired to select the k greatest or smallest data in a set of data.
  • the logic circuit shown in FIG. 3 is given by way of example. It is possible to obtain the same results with a large number of various logic circuits. The functions of these circuits can also be achieved with a programmed microprocessor appropriately programmed and associated with the memories.
  • the priority modules MP have been described as having a fixed content, but it can be modified like the content of any other modules for obtaining variable priority orders.

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  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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US08/267,293 1991-02-21 1994-06-28 Circuit and a method for selecting the kappa greatest data in a data sequence Expired - Lifetime US5421010A (en)

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US08/267,293 US5421010A (en) 1991-02-21 1994-06-28 Circuit and a method for selecting the kappa greatest data in a data sequence

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FR9102301A FR2673301B1 (fr) 1991-02-21 1991-02-21 Circuit et procede de selection des k plus grandes donnees d'une suite de donnees.
FR91/02301 1991-02-21
US83866892A 1992-02-20 1992-02-20
US08/267,293 US5421010A (en) 1991-02-21 1994-06-28 Circuit and a method for selecting the kappa greatest data in a data sequence

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JP (1) JP3218669B2 (fr)
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Cited By (1)

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Publication number Priority date Publication date Assignee Title
EP0984355A3 (fr) * 1998-09-01 2002-06-05 Siemens Aktiengesellschaft Appareil pour la détermination rapide des n valeurs les plus grandes, ou n est un nombre présélectionné

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EP0273802A2 (fr) * 1986-12-02 1988-07-06 Sgs-Thomson Microelectronics S.A. Filtre numérique de rang K, et procédé de filtrage correspondant

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JPH0310486A (ja) * 1989-06-07 1991-01-18 Matsushita Electric Ind Co Ltd 動画像符号化装置

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US4317182A (en) * 1979-03-01 1982-02-23 Nissan Motor Company, Limited Signal averaging device
EP0273802A2 (fr) * 1986-12-02 1988-07-06 Sgs-Thomson Microelectronics S.A. Filtre numérique de rang K, et procédé de filtrage correspondant

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Title
"A Bit-serial Device for Extracting a Vector Element of a Specified Rank", C. K. Yuen, Digital Processes, vol. 6, No. 2-3, 1980, pp. 207-210.
A Bit serial Device for Extracting a Vector Element of a Specified Rank , C. K. Yuen, Digital Processes, vol. 6, No. 2 3, 1980, pp. 207 210. *
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0984355A3 (fr) * 1998-09-01 2002-06-05 Siemens Aktiengesellschaft Appareil pour la détermination rapide des n valeurs les plus grandes, ou n est un nombre présélectionné
US6446101B1 (en) 1998-09-01 2002-09-03 Siemens Aktiengesellschaft Apparatus for fast determination of a prescribable number of highest value signals

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JP3218669B2 (ja) 2001-10-15
FR2673301B1 (fr) 1994-02-18
DE69225260D1 (de) 1998-06-04
EP0500481B1 (fr) 1998-04-29
DE69225260T2 (de) 1998-11-19
EP0500481A1 (fr) 1992-08-26
JPH05150945A (ja) 1993-06-18
FR2673301A1 (fr) 1992-08-28

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