US7614565B2 - Semiconductor device and control method in semiconductor device - Google Patents

Semiconductor device and control method in semiconductor device Download PDF

Info

Publication number
US7614565B2
US7614565B2 US11/287,231 US28723105A US7614565B2 US 7614565 B2 US7614565 B2 US 7614565B2 US 28723105 A US28723105 A US 28723105A US 7614565 B2 US7614565 B2 US 7614565B2
Authority
US
United States
Prior art keywords
load
output
terminal
data
outputting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US11/287,231
Other languages
English (en)
Other versions
US20070040038A1 (en
Inventor
Kazunori Kasuga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Assigned to FUJITSU LIMITED reassignment FUJITSU LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KASUGA, KAZUNORI
Publication of US20070040038A1 publication Critical patent/US20070040038A1/en
Application granted granted Critical
Publication of US7614565B2 publication Critical patent/US7614565B2/en
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

Definitions

  • the present invention relates to a semiconductor device and a control method in a semiconductor device, and more particularly to a semiconductor device in which information will not be analyzed even if an analyzer is connected.
  • an information processing device wherein data in memory is deleted when detachment of the memory is detected is disclosed (e.g. Japanese Patent Application Laid-Open No. 2002-73422).
  • a processing device wherein a decoding key to read confidential data of a storage device is stored on another storage device, and the decoding key becomes invalid if the storage device storing the confidential data is removed, is disclosed (e.g. Japanese Patent Application Laid-Open No. H9-16477).
  • an IC card wherein the content of the memory is erased if the thin film battery is removed or the card itself is opened (e.g. Japanese Patent Application Laid-Open No. H11-328036, No. 2001-195307, and No. H10-320293), and a device with a safety information external access prevention function, wherein the content of the memory is reset if stress is applied to the piezo-electrical material (e.g. Japanese Patent Application Laid-Open No. H5-88986), are also available.
  • the present invention is a semiconductor device, comprising a load detection portion for measuring the load quantity of the load connected to a terminal, and outputting a control signal if the load quantity substantially matches a reference load, and an output control portion for stopping the output of data from the terminal or outputting a specific logic to the terminal, responding to the control signal.
  • the load detection portion further comprises a reference load output portion for outputting the reference load, and a comparison portion for comparing the measured load quantity and the load quantity from the reference load output means, and outputting the control signal according to the comparison result.
  • the load detection portion further comprises a reference register for outputting the reference load which is digitized, a digital conversion portion for converting the measured load quantity into a digital value, and a comparison portion for comparing the load quantity which has been converted into a digital value and the reference load from the reference register, and outputting the control signal according to the comparison result.
  • the reference load is a load quantity when a probe of an analyzer, for reading and analyzing the data, is connected to the terminal.
  • the semiconductor device further comprises a storage portion for storing the data, wherein the output control portion stops the output of the data stored in the storage portion from the terminal, or outputs a specific logic, responding to the control signal.
  • the present invention is a control method in a semiconductor device comprising a load detection portion for measuring load quantity of a load connected to a terminal and an output control portion for outputting data from the terminal, comprising the steps of outputting a control signal from the load detection portion if the measured load quantity substantially matches a reference load, and stopping the output of the data from the terminal by the output control portion or outputting a specific logic from the output control portion to the terminal, responding to the control signal.
  • a semiconductor device with which information is not analyzed even if an analyzer or a measurement device is connected, and a control method in the semiconductor device can be provided.
  • FIG. 1 is a diagram depicting a configuration example of a semiconductor integrated circuit to which the present invention is applied;
  • FIG. 2 is a diagram depicting a configuration example of a load detection circuit, reference load output section and comparison circuit
  • FIG. 3 is a diagram depicting a configuration example of an input and output buffer
  • FIG. 4 is a diagram depicting an operation waveform
  • FIG. 5 is a diagram depicting a configuration example of an input and output buffer
  • FIG. 6 is a diagram depicting a configuration example of another semiconductor integrated circuit to which the present invention is applied.
  • FIG. 7 is a diagram depicting an operation waveform.
  • FIG. 1 is a drawing depicting a configuration example of a semiconductor integrated circuit 1 to which the semiconductor device according to the present invention is applied.
  • the semiconductor integrated circuit 1 comprises a memory cell 10 , command decoder 20 , input and output buffer 30 , load detection circuit 40 , reference load output section 50 and comparison circuit 60 .
  • the memory cell 10 is a storage device where various data is stored. In the present embodiment, such data as confidential information and personal information are also stored.
  • the command decoder 20 is connected to the input and output buffer 30 , and outputs enable signals for indicating a data write and data read to the memory cell 10 (“WriteEnable” and “ReadEnable” respectively).
  • the input and output buffer 30 is also connected to the memory cell 10 and the terminal DQ.
  • the input and output buffer 30 temporarily stores the data which is input from the terminal DQ, and then outputs it to the memory cell 10 .
  • the input and output buffer 30 also temporarily stores data which is read from the memory cell 10 , and then outputs it to the terminal DQ. These operations are executed according to enable signals (“WriteEnable” and “ReadEnable” respectively).
  • the load detection circuit 40 is connected to the terminal DQ.
  • the load detection circuit 40 detects the load value (e.g. load current or load capacity) of the load portion 100 connected to the terminal DQ, and outputs the value.
  • the load portion 100 is an IC for the controller or a probe of an analyzer, for example.
  • the reference load output section 50 outputs the reference load.
  • the reference load is a numeric value when the load value of the load portion 100 and the load of the probe of the analyzer are added.
  • the comparison circuit 60 is connected to the load detection circuit 40 and the reference load output section 50 , and is also connected to the input and output buffer 30 .
  • the comparison circuit 60 compares the load from the load detection circuit 40 and the reference load from the reference load output section 50 , and outputs the control signal to the input and output buffer 30 if both values match. In other words, if the probe is connected to the terminal DQ, the control signal is output from the comparison circuit 60 .
  • the input and output buffer 30 stops the output of the data which was read from the memory cell 10 or outputs a specific fixed logic (“0” or “1”) to the terminal DQ. In other words, if the probe is connected to the terminal DQ, the output of the data from the terminal DQ is stopped, or a specific logic is output, so that the data stored in the memory cell 10 cannot be read.
  • FIG. 2 is a diagram depicting a detailed configuration example of a circuit including the load detection circuit 40 , reference load output section 50 and comparison circuit 60 . These circuits, 40 , 50 and 60 , are disposed for the number of terminals (n+1 in the case of the example in FIG. 2 ).
  • the circuit 40 , 50 or 60 is comprised of an input resistor 41 , comparator 42 , output resistor 43 , first reference resistor 44 and second reference resistor 45 .
  • One end of the input resistor 41 is connected to the terminal DQ 0 and the other end is connected to the comparator 42 .
  • One end of the first reference resistor 44 is connected between the input resistor 41 and the comparator 42 .
  • the output resistor 43 is disposed at the output side of the comparator 42 such that the output of the output resistor 43 is also inputted to the comparator 42 . And one end of the second reference resistor 45 , of which the other end is grounded, is connected between the output of the output resistor 43 and the comparator 42 .
  • the comparator 42 of which the plus (+) side is the reference voltage, outputs the input current which is inputted to the terminal DQ 0 , if the voltage value of the minus ( ⁇ ) side is higher than the reference voltage.
  • the current to be input to the terminal DQ 0 when a probe is connected to the terminal DQ is different from when an IC for the controller is connected (normal status). Therefore if the reference voltage is adjusted so that this current is outputted when a probe is connected to the terminal DQ, the circuits 40 , 50 and 60 output a predetermined voltage value only at this time. For example, if a probe is connected, the circuits 40 , 50 and 60 output a voltage value corresponding to logic “HIGH”, and outputs a voltage value corresponding to “LOW” otherwise.
  • the reference voltage in the comparator 42 is adjusted by changing the resistance values of the output resistor 43 and second reference resistor 45 .
  • the reference voltage can be adjusted.
  • the first reference voltage 44 can also be adjusted from the outside.
  • the reference voltage at the plus side of the comparator 42 becomes the reference load, and is compared with the voltage value at the minus side, so the comparator 42 corresponds to the load detection circuit 40 and the comparison circuit 60 , and the output resistor 43 and the second reference resistor 45 correspond to the reference load output section 50 .
  • an OR circuit 46 and a latch circuit comprised of two NOR circuits, 47 and 48 are disposed.
  • the OR circuit 46 outputs the signal Comp, which indicates whether a probe is connected to the terminals DQ 0 -DQn, the output thereof is latched by the latch circuit, and the detection signal Detect is output.
  • the signal Comp becomes “HIGH” and the detection signal Detect becomes “LOW”.
  • This output signal Comp or the detection signal Detect corresponds to the control signal which is outputted from the comparison circuit 60 to the input and output buffer 30 .
  • FIG. 3 is a diagram depicting a configuration example of the input and output buffer 30 . This is a block diagram in the case of stopping the output of data read from the memory cell 10 .
  • the input and output buffer 30 is comprised of the NAND circuit 31 , and the first and second buffer circuits 32 , 33 .
  • the NAND circuit 31 is connected to the command decoder 20 and the NOR circuit 47 (see FIG. 2 ), to which the Enable signal from the command decoder 20 and the output signal from the comparison circuit 60 are input, and from which the output signal OutputEnable is output.
  • the first buffer 32 stores the output from the memory cell 10 , and outputs it to the terminals DQ 0 -DQn.
  • the first buffer 32 is a buffer corresponding to the data read from the memory cell 10 .
  • the first buffer 32 has a three-state circuit configuration, and can enter “HIGH”, “LOW” and high impedance (hereafter “HIGH-Z”) status. Whether the first buffer 32 can enter “HIGH-Z” status or not depends on the output signal OutputEnable.
  • the first buffer 32 enters “HIGH-Z” status, where electric connection is cleared, and output to the terminals DQ 0 -DQn is stopped.
  • the output signal OutputEnable is “LOW”, logic according to the input is output.
  • the second buffer 33 as well can enter three statuses: “HIGH-Z”, “LOW”, and “HIGH”.
  • the second buffer 33 is a buffer corresponding to the writing to the memory cell 10 .
  • FIG. 4 is a waveform diagram depicting the operation of each signal in the configurations shown in FIG. 2 and FIG. 3 . This is an example of the case if the probe is connected in normal status to the terminal DQ and then the status returns to normal status again.
  • the ReadEnable signal which indicates the reading from the memory cell 10
  • the output signal OutputEnable of the NAND circuit 31 is “LOW” since the input is “HIGH”.
  • a probe is connected to the terminal DQ 0 , for example, in this status, a signal to indicate the connection of the probe is output from the circuits 40 , 50 and 60 , so the output signal Comp becomes “HIGH”. And the detection signal Detect becomes “LOW”.
  • the detection signal “LOW” is input to the NAND circuit 31 in a status where the ReadEnable signal “HIGH” is being outputted from the command decoder 20 , the output signal OutputEnable becomes “HIGH”. Therefore the first buffer circuit 32 outputs “HIGH-Z”, and the reading from the memory cell 10 is stopped. In other words, if a probe is connected to the terminal DQ 0 , the reading from the memory cell 10 is stopped.
  • the status returns to normal, and the output signal Comp becomes “LOW”.
  • the RESET signal is input from the input end of the NOR circuit 48 shown in FIG. 2 (“HIGH”), and each circuit is returned to normal status.
  • operation performed is the same as the above mentioned normal status.
  • FIG. 5 is a diagram depicting a configuration example of the input and output buffer 30 , just like FIG. 4 , where a fixed logic is continuously output.
  • the input and output buffer 30 is comprised of an NOR circuit 35 , AND circuit 36 , and first and second buffer circuits 37 and 38 .
  • the NOT circuit 35 is connected to the command decoder 20 , to which the Enable signal is inputted from the command decoder 20 , and from which the OutputEnable signal is outputted.
  • the AND circuit 36 is connected to the memory cell 10 and the NOR circuit 47 (see FIG. 2 ), and decides the logic according to the output signal from the comparison circuit 60 .
  • the first buffer 37 stores the output from the AND circuit 36 and outputs it to the terminals DQ 0 -DQn.
  • the first buffer 37 is a buffer corresponding to the reading of the data from the memory cell 10 .
  • the first buffer 37 is a three-state circuit configuration, and can enter “HIGH”, “LOW” and high impedance (hereafter “HIGH-Z”) statuses. Whether the first buffer 37 can enter “HIGH-Z” status or not depends on the output signal OutputEnable.
  • the first buffer 32 enters “HIGH-Z” status, where electronic connection is cleared, and output to the terminals DQ 0 -DQn is stopped.
  • the output signal OutputEnable is “LOW”, logic according to the input is output.
  • the second buffer 38 as well can enter the three statuses: “HIGH-Z”, “LOW”, and “HIGH” based on the signal from the command decoder 20 .
  • the second buffer 38 is a buffer corresponding to the writing to the memory cell 10 .
  • FIG. 7 is a waveform diagram depicting the operation of each signal in the configurations shown in FIG. 2 and FIG. 5 . This is an example of the case if a probe is connected to the terminal DQ in normal status, and then the status is returned to normal status again.
  • a probe is connected to the terminal DQ 0 , for example, in this status, a signal to indicate the connection of the probe is outputted from the circuits 40 , 50 and 60 , so the output signal Comp becomes “HIGH”. And the detection signal Detect becomes “LOW”.
  • the detection signal “LOW” is inputted to the AND circuit 36 in a status where the ReadEnable signal “HIGH” is being outputted from the command decoder 20 , the output signal thereof becomes “LOW” regardless the logic of the memory cell 10 . Therefore the first buffer circuit 37 outputs “LOW”, and the reading from the memory cell 10 is fixed to “LOW”. In other words, if a probe is connected to the terminal DQ 0 , the reading from the memory cell 10 maintains “LOW” all the time.
  • the status returns to normal status and the output signal Comp becomes “LOW”.
  • the RESET signal is input from the input end of the NOR circuit 48 shown in FIG. 2 (“HIGH”), and each circuit is returned to normal status.
  • the operation performed is the same as the above mentioned normal status.
  • the present invention can also be applied to the configuration shown in FIG. 6 .
  • the load value detected by the load detection circuit 40 is converted into a digital value by the AD conversion circuit 70 , and is output to the digital comparison circuit 61 .
  • the digital value to indicate a load if a probe is connected to the terminal DQ, is outputted from the reference register 51 , and the digital comparison circuit 61 compares this reference value and the digital value from the AD conversion circuit 70 , and outputs the control signal if they match.
  • the output from the memory cell 10 is stopped, or a fixed specific logic is continuously outputted if this control signal is input, so that the data stored in the memory cell 10 cannot be read. Since data is not output from the terminal DQ to the analyzer if the probe is connected, the data cannot be analyzed.
  • the circuit shown in FIG. 2 is an example, and any circuit configuration may be used only if the output signal Comp or the detection signal Detect, to indicate whether a probe is connected or not, can be output.
  • the OR circuit 46 may be an AND circuit, or the latch circuit (NOR circuit 47 or 48 ) may be removed.
  • any circuit configuration can be used only if the output from the memory cell 10 can be stopped and a specific logic can be continuously output.
  • an AND circuit may be used instead of the NAND circuit 31 . In any case, the same functional effect as the above mentioned example is implemented.
  • the semiconductor integrated circuit 1 shown in FIG. 1 and FIG. 5 can be applied to an information portable terminal, such as a notebook type personal computer, PDA and portable telephone, and in this case as well, the same functional effect as the above mentioned example is implemented.
  • an information portable terminal such as a notebook type personal computer, PDA and portable telephone

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Storage Device Security (AREA)
  • Tests Of Electronic Circuits (AREA)
US11/287,231 2005-08-19 2005-11-28 Semiconductor device and control method in semiconductor device Expired - Fee Related US7614565B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005-238617 2005-08-19
JP2005238617A JP4754903B2 (ja) 2005-08-19 2005-08-19 半導体装置、及び半導体装置における制御方法

Publications (2)

Publication Number Publication Date
US20070040038A1 US20070040038A1 (en) 2007-02-22
US7614565B2 true US7614565B2 (en) 2009-11-10

Family

ID=37766567

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/287,231 Expired - Fee Related US7614565B2 (en) 2005-08-19 2005-11-28 Semiconductor device and control method in semiconductor device

Country Status (3)

Country Link
US (1) US7614565B2 (ko)
JP (1) JP4754903B2 (ko)
KR (1) KR100683096B1 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0223327D0 (en) * 2002-10-08 2002-11-13 Ranier Ltd Artificial spinal disc
KR101075495B1 (ko) * 2010-07-06 2011-10-21 주식회사 하이닉스반도체 반도체 모듈에 포함된 다수의 반도체 장치를 선택하는 회로 및 그 동작방법
JP6358497B2 (ja) * 2014-04-19 2018-07-18 Ｔｉａｎｍａ Ｊａｐａｎ株式会社 制御装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0509567A2 (en) 1991-03-28 1992-10-21 Koninklijke Philips Electronics N.V. Device with protection against access to secure information
JPH0916477A (ja) 1995-06-30 1997-01-17 Oki Electric Ind Co Ltd 機密性データの処理方法と処理装置
JPH10320293A (ja) 1997-05-19 1998-12-04 Rohm Co Ltd Ｉｃカードおよびｉｃチップモジュール
JPH11328036A (ja) 1998-05-20 1999-11-30 Nippon Telegr & Teleph Corp <Ntt> Ｉｃカード
JP2001195307A (ja) 2000-01-06 2001-07-19 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
JP2001202167A (ja) 2000-01-20 2001-07-27 Toyo Commun Equip Co Ltd コンピュータ及びその制御方法
JP2002073422A (ja) 2000-09-05 2002-03-12 Sharp Corp 情報処理装置
US20050060991A1 (en) * 2003-09-19 2005-03-24 Nissan Motor Co., Ltd. Filter regeneration in engine exhaust gas purification device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63208145A (ja) * 1987-02-25 1988-08-29 Hitachi Ltd Ｉｃカ−ド
JP2811142B2 (ja) * 1992-04-30 1998-10-15 アツデン株式会社 消費電力管理システム
JP3654938B2 (ja) * 1994-09-20 2005-06-02 大日本印刷株式会社 電話機
JPH11120309A (ja) * 1997-10-15 1999-04-30 Hitachi Ltd 耐改竄機能付通信装置
JP2000347848A (ja) * 1999-03-30 2000-12-15 Sony Corp 半導体ｉｃ、情報処理方法、情報処理装置、並びにプログラム格納媒体
KR20030026551A (ko) * 2001-09-26 2003-04-03 삼성전자주식회사 메모리 칩의 출력 구동회로 보정 기능을 구비한 메모리 모듈
JP3983521B2 (ja) * 2001-11-14 2007-09-26 シャープ株式会社 半導体装置およびｉｃカード
DE60310139T2 (de) * 2003-01-14 2007-09-27 Koninklijke Philips Electronics N.V. Erkennung von manipulation an einer chipkartenschnittstelle
JP4345380B2 (ja) 2003-07-02 2009-10-14 富士電機システムズ株式会社 電動機の駆動制御装置
KR100564573B1 (ko) * 2003-08-29 2006-03-29 삼성전자주식회사 데이터 저장 시스템에서의 데이터 보호 방법 및 이를이용한 디스크 드라이브

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0509567A2 (en) 1991-03-28 1992-10-21 Koninklijke Philips Electronics N.V. Device with protection against access to secure information
JPH0588986A (ja) 1991-03-28 1993-04-09 Philips Gloeilampenfab:Nv 安全情報外部アクセス防止付装置
JPH0916477A (ja) 1995-06-30 1997-01-17 Oki Electric Ind Co Ltd 機密性データの処理方法と処理装置
JPH10320293A (ja) 1997-05-19 1998-12-04 Rohm Co Ltd Ｉｃカードおよびｉｃチップモジュール
US6802008B1 (en) 1997-05-19 2004-10-05 Rohm Co., Ltd. IC card and IC chip module
JPH11328036A (ja) 1998-05-20 1999-11-30 Nippon Telegr & Teleph Corp <Ntt> Ｉｃカード
JP2001195307A (ja) 2000-01-06 2001-07-19 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
JP2001202167A (ja) 2000-01-20 2001-07-27 Toyo Commun Equip Co Ltd コンピュータ及びその制御方法
JP2002073422A (ja) 2000-09-05 2002-03-12 Sharp Corp 情報処理装置
US20050060991A1 (en) * 2003-09-19 2005-03-24 Nissan Motor Co., Ltd. Filter regeneration in engine exhaust gas purification device

Also Published As

Publication number Publication date
KR100683096B1 (ko) 2007-02-16
JP4754903B2 (ja) 2011-08-24
US20070040038A1 (en) 2007-02-22
JP2007052709A (ja) 2007-03-01

Similar Documents

Publication Publication Date Title
US7305596B2 (en) Nonvolatile memory and nonvolatile memory apparatus
US6311299B1 (en) Data compression circuit and method for testing embedded memory devices
US8316242B2 (en) Cryptoprocessor with improved data protection
US7483328B2 (en) Voltage glitch detection circuits and methods thereof
US20070164778A1 (en) Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same
WO2006036443A2 (en) Method and apparatus for protecting an integrated circuit from erroneous operation
US9599645B2 (en) High speed clock cycle rate digital voltage monitor with triggered tracing for integrated circuits
US5898634A (en) Integrated circuit with supply voltage detector
JP3215566B2 (ja) 半導体記憶装置
TW533411B (en) Burst read incorporating output based redundancy
US7614565B2 (en) Semiconductor device and control method in semiconductor device
US7420866B2 (en) Method and system of operating mode detection
US7363190B2 (en) Sensor control circuit
US20050044403A1 (en) Detection circuit for a smart card
US6456539B1 (en) Method and apparatus for sensing a memory signal from a selected memory cell of a memory device
US5825204A (en) Apparatus and method for a party check logic circuit in a dynamic random access memory
US11327882B2 (en) Method and apparatus for eliminating bit disturbance errors in non-volatile memory devices
US7266015B2 (en) Redundancy substitution method, semiconductor memory device and information processing apparatus
JP2741887B2 (ja) 特殊試験機能回路を備える半導体装置
US7710762B2 (en) Device for protecting SRAM data
US20050117396A1 (en) Semiconductor storage apparatus and microcomputer having the same
US20070152732A1 (en) Method and apparatus to detect electrical overstress of a device
US20070247182A1 (en) Protection of security key information
KR100222576B1 (ko) 아이씨 카드 회로 및 이의 테스트 방법
US20080150570A1 (en) Over clocking detector

Legal Events

Date Code Title Description
AS Assignment

Owner name: FUJITSU LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KASUGA, KAZUNORI;REEL/FRAME:017289/0279

Effective date: 20051031

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20211110