USH73H - Integrated circuit packages - Google Patents

Integrated circuit packages Download PDF

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Publication number
USH73H
USH73H US06/526,413 US52641383A USH73H US H73 H USH73 H US H73H US 52641383 A US52641383 A US 52641383A US H73 H USH73 H US H73H
Authority
US
United States
Prior art keywords
chip
wires
pads
layer
rtv
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US06/526,413
Other languages
English (en)
Inventor
Kenneth K. Claasen
Ronald N. Graver
Frank P. Pelletier
Kurt M. Striny
Ronald J. Wozniak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Bell Labs USA
AT&T Corp
Original Assignee
AT&T Bell Laboratories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Bell Laboratories Inc filed Critical AT&T Bell Laboratories Inc
Priority to US06/526,413 priority Critical patent/USH73H/en
Assigned to BELL TELEPHONE LABORATORIES, INCORPORATED reassignment BELL TELEPHONE LABORATORIES, INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: CLAASEN, KENNETH K., GRAVER, RONALD N., PELLETIER, FRANK P., STRINY, KURT M., WOZNIAK, RONALD J.
Priority to KR1019840003623A priority patent/KR850002676A/ko
Priority to JP59175338A priority patent/JPS6072251A/ja
Application granted granted Critical
Publication of USH73H publication Critical patent/USH73H/en
Abandoned legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H10W72/01515—Forming coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • This invention relates to semiconductor devices and in particular to a package including wire-bonded semiconductor chips.
  • DIP dual-in-line
  • a semiconductor device comprising a semiconductor chip electrically interconnected to metal leads by means of wires extending from pads on the chip to the leads.
  • the wires include arched portions.
  • a thick, protective layer which comprises a material having a large expansion coefficient and a low shear modulus, is formed over the surface of the chip to a thickness which covers at least the part of the arched portion of the wires where the slope of the wires is reduced to less than 45° relative to the semiconductor chip surface.
  • a plastic encapsulating material surrounds the chip, protective layer and a portion of the leads.
  • FIG. 1 is a cross-sectional view of a semiconductor device in accordance with one embodiment of the invention.
  • FIG. 2 is a graph showing the reliability of devices in accordance with the same embodiment of the invention as compared to other devices.
  • a semiconductor IC chip, 10, is provided with bonding pads, 11 and 12, on one major surface.
  • the pads, 11 and 12 are electrically interconnected to leads, 13 and 14, respectively, which extend out from the package on two sides of the chip for connection to external circuitry.
  • the electrical interconnection is made by wires, 15 and 16, which are bonded to their respective pads, 11 and 12, by means of standard ball bonds, 17 and 18, which were formed from the wires by heating according to standard techniques.
  • the opposite major surface of the chip was bonded to a metal plate (die support paddle), 24, which is part of the lead frame.
  • the chip was 180 mils long, 180 mils wide and 10 mils thick.
  • the wires were approximately 60 mils long and the leads were approximately 750 mils long.
  • the pads were approximately 5 mils ⁇ 5 mils.
  • each wire includes an arch portion, 25 and 26, with a portion of the arch, 19 and 20, where the slope of the wire goes from essentially vertical (typically approximately 100° to the surface to a slope of less than 45° to the semiconductor surface.
  • the chip, 10, along with the wires, 15 and 16, and at least a portion of the leads, 13 and 14, are encapsulated in a plastic material, 22, to form a dual-in-line package.
  • the semiconductor chip, prior to encapsulation is covered by a thick, protective layer, 21, which in this example is RTV silicone rubber.
  • the RTV coating of the present invention is thick enough, in this example approximately 10 mils in the area over the pads, so as to cover the portions, 19 and 20, of the arched portions of wires.
  • the stresses and strains in the wire are caused by the expansion and the contraction of the wires and materials, 10 and 22.
  • FIG. 2 illustrates the increased reliability of the present package in terms of the number of cycles to median life failure for three types of packages when subjected to temperature cycles of -40° C. to 150° C. of approximately 10 minutes per cycle. All packages were 40 lead DIP packages with identical chips encapsulated in plastic. However, one type (curve A) had no RTV applied, one type (curve B) had a thin (1-2 mil) layer of RTV applied and the third type (curve C) had RTV applied in accordance with the invention to a cured thickness of 10 mils in the area over the chip pads. (It will be appreciated that the RTV has a domed shape with a maximum thickness over the middle portion of the chip.
  • the important thickness is that over the area of the contact pads, 11 and 12, which are situated at the edges of the chip.
  • the maximum height of RTV is approximately 25 mils over the middle of the chip.
  • the ordinate shows the coefficient of thermal expansion of different plastic encapsulants employed and the abscissa shows the number of cycles to failure of the median number of devices in each group tested (a failure for a device occurs when one of the wire bonds break).
  • a typical sample size was approximately 60 devices.
  • the RTV was a standard, commercially available type, such as that sold by Dow Corning under the designation DC6550 which was diluted with xylene.
  • the RTV was applied with a dispenser and cured at room temperature for 2 hours and at 125° C. for 6-8 hours.
  • the plastic encapsulant was also a standard, commercially available material such as that sold by Plascon under the designation 3200 LS.
  • the plastic was molded around the structure at a temperature of 150°-175° C. for 2-3 minutes in a standard transfer molding press. As the package cools down to room temperature, the RTV shrinks and an air gap, 23, was formed between the RTV and encapsulant.
  • the formation of this air gap is important since it relieves pressure on the wire bonds by giving some room for mobility of the RTV layer.
  • the air gap has a dimension in the range 1-5 mils at room temperature over the area of the chip pads.
  • the layer should preferably have a large expansion coefficient to form the air gap and a low shear modulus so that movement of the layer causes a minimum stress on the wires. It is recommended that the expansion coefficient be at least 200ppm/°C. and the shear modulus be no greater than 100 psi at -40° C. to 150° C. In general, the thickness of the protective layer should be in the range 6-15 mils over the area of the chip pads.
  • the plastic encapsulant could be any material usually used for encapsulating integrated circuits.
  • a low expansion coefficient material is preferred, and the encapsulant will typically have an expansion coefficient which is less than 25 ppm/°C. from -40° C. to 125° C.

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
US06/526,413 1983-08-25 1983-08-25 Integrated circuit packages Abandoned USH73H (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US06/526,413 USH73H (en) 1983-08-25 1983-08-25 Integrated circuit packages
KR1019840003623A KR850002676A (ko) 1983-08-25 1984-06-26 집적회로 칩팩키지
JP59175338A JPS6072251A (ja) 1983-08-25 1984-08-24 封入された半導体デバイス

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/526,413 USH73H (en) 1983-08-25 1983-08-25 Integrated circuit packages

Publications (1)

Publication Number Publication Date
USH73H true USH73H (en) 1986-06-03

Family

ID=24097238

Family Applications (1)

Application Number Title Priority Date Filing Date
US06/526,413 Abandoned USH73H (en) 1983-08-25 1983-08-25 Integrated circuit packages

Country Status (3)

Country Link
US (1) USH73H (ja)
JP (1) JPS6072251A (ja)
KR (1) KR850002676A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5331205A (en) * 1992-02-21 1994-07-19 Motorola, Inc. Molded plastic package with wire protection
US5917246A (en) * 1995-03-23 1999-06-29 Nippondenso Co., Ltd. Semiconductor package with pocket for sealing material
US20030024735A1 (en) * 2001-08-01 2003-02-06 Volker Strutz Protective device for subassemblies and method for producing a protective device
US20030119224A1 (en) * 1999-08-30 2003-06-26 Corisis David J. Semiconductor package
US7651891B1 (en) * 2007-08-09 2010-01-26 National Semiconductor Corporation Integrated circuit package with stress reduction
US20120061919A1 (en) * 2008-08-13 2012-03-15 Temic Automotive Of North America, Inc. Seal Apparatus and Method of Manufacturing the Same
US20190019784A1 (en) * 2015-09-04 2019-01-17 Kabushiki Kaisha Toshiba Semiconductor device and optical coupling device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2850687A (en) 1953-10-13 1958-09-02 Rca Corp Semiconductor devices
US3670091A (en) 1971-05-20 1972-06-13 Sqrague Electric Co Encapsulated electrical components with protective pre-coat containing collapsible microspheres
US3763403A (en) 1972-03-01 1973-10-02 Gen Electric Isolated heat-sink semiconductor device
US3839660A (en) 1973-02-05 1974-10-01 Gen Motors Corp Power semiconductor device package
US4048670A (en) 1975-06-30 1977-09-13 Sprague Electric Company Stress-free hall-cell package
US4169271A (en) 1977-01-27 1979-09-25 Tokyo Shibaura Electric Co., Ltd. Semiconductor device including a thermal fuse encapsulated in a droplet of silicone rubber

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2850687A (en) 1953-10-13 1958-09-02 Rca Corp Semiconductor devices
US3670091A (en) 1971-05-20 1972-06-13 Sqrague Electric Co Encapsulated electrical components with protective pre-coat containing collapsible microspheres
US3763403A (en) 1972-03-01 1973-10-02 Gen Electric Isolated heat-sink semiconductor device
US3839660A (en) 1973-02-05 1974-10-01 Gen Motors Corp Power semiconductor device package
US4048670A (en) 1975-06-30 1977-09-13 Sprague Electric Company Stress-free hall-cell package
US4169271A (en) 1977-01-27 1979-09-25 Tokyo Shibaura Electric Co., Ltd. Semiconductor device including a thermal fuse encapsulated in a droplet of silicone rubber

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5331205A (en) * 1992-02-21 1994-07-19 Motorola, Inc. Molded plastic package with wire protection
US5917246A (en) * 1995-03-23 1999-06-29 Nippondenso Co., Ltd. Semiconductor package with pocket for sealing material
US20030119224A1 (en) * 1999-08-30 2003-06-26 Corisis David J. Semiconductor package
US7226813B2 (en) * 1999-08-30 2007-06-05 Micron Technology, Inc. Semiconductor package
US20030024735A1 (en) * 2001-08-01 2003-02-06 Volker Strutz Protective device for subassemblies and method for producing a protective device
US7235873B2 (en) * 2001-08-01 2007-06-26 Infineon Technologies Ag Protective device for subassemblies and method for producing a protective device
US7651891B1 (en) * 2007-08-09 2010-01-26 National Semiconductor Corporation Integrated circuit package with stress reduction
US20120061919A1 (en) * 2008-08-13 2012-03-15 Temic Automotive Of North America, Inc. Seal Apparatus and Method of Manufacturing the Same
US8689438B2 (en) * 2008-08-13 2014-04-08 Continental Automotive Systems, Inc. Seal apparatus and method of manufacturing the same
US20190019784A1 (en) * 2015-09-04 2019-01-17 Kabushiki Kaisha Toshiba Semiconductor device and optical coupling device
US10833055B2 (en) * 2015-09-04 2020-11-10 Kabushiki Kaisha Toshiba Semiconductor device and optical coupling device

Also Published As

Publication number Publication date
KR850002676A (ko) 1985-05-15
JPS6072251A (ja) 1985-04-24

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