UST100501I4 - Integrated circuit layout utilizing separated active circuit and wiring regions - Google Patents

Integrated circuit layout utilizing separated active circuit and wiring regions Download PDF

Info

Publication number: UST100501I4
Authority: US; United States
Prior art keywords: insulating layer; apertures; sets; exposed; cells
Prior art date: 1977-09-06
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Pending

Application number

US06/058,360

Other languages

English (en)

Inventor

John Balyoz

Algirdas J. Gruodis

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Individual

Original Assignee

Individual

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1977-09-06

Filing date

1979-07-17

Publication date

1981-04-07

1979-07-17 Application filed by Individual filed Critical Individual

1981-04-07 Application granted granted Critical

1981-04-07 Publication of UST100501I4 publication Critical patent/UST100501I4/en

Status Pending legal-status Critical Current

Links

Images

Classifications

- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/901—Masterslice integrated circuits comprising bipolar technology
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/43—Layouts of interconnections

Landscapes

Design And Manufacture Of Integrated Circuits (AREA)
Semiconductor Integrated Circuits (AREA)
Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

US06/058,360 1977-09-06 1979-07-17 Integrated circuit layout utilizing separated active circuit and wiring regions Pending UST100501I4 (en)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
US83071577A	1977-09-06	1977-09-06

Related Parent Applications (1)

Application Number	Title	Priority Date	Filing Date
US83071577A Continuation	1977-09-06	1977-09-06

Publications (1)

Publication Number	Publication Date
UST100501I4 true UST100501I4 (en)	1981-04-07

Family

ID=25257547

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
US06/058,360 Pending UST100501I4 (en)	1977-09-06	1979-07-17	Integrated circuit layout utilizing separated active circuit and wiring regions

Country Status (5)

Country	Link
US (1)	UST100501I4 (fr)
EP (1)	EP0001209A1 (fr)
JP (1)	JPS5441088A (fr)
CA (1)	CA1102009A (fr)
IT (1)	IT1110167B (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4623911A (en)	1983-12-16	1986-11-18	Rca Corporation	High circuit density ICs
US4748494A (en)	1985-04-19	1988-05-31	Hitachi, Ltd.	Lead arrangement for reducing voltage variation
US10878158B2 (en) *	2018-07-16	2020-12-29	Taiwan Semiconductor Manufacturing Company, Ltd.	Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4249193A (en) *	1978-05-25	1981-02-03	International Business Machines Corporation	LSI Semiconductor device and fabrication thereof
JPS55138865A (en) *	1979-04-17	1980-10-30	Nec Corp	Semiconductor device
JPS55163859A (en) *	1979-06-07	1980-12-20	Fujitsu Ltd	Manufacture of semiconductor device
FR2524206B1 (fr) *	1982-03-26	1985-12-13	Thomson Csf Mat Tel	Circuit integre prediffuse, et procede d'interconnexion des cellules de ce circuit
US4737836A (en) *	1983-12-30	1988-04-12	International Business Machines Corporation	VLSI integrated circuit having parallel bonding areas
JPH0758761B2 (ja) *	1983-12-30	1995-06-21	インターナショナル・ビジネス・マシーンズ・コーポレーション	半導体集積回路チップ
EP0154346B1 (fr) *	1984-03-08	1991-09-18	Kabushiki Kaisha Toshiba	Dispositif à circuit intégré semi-conducteur
JPS6288337A (ja) *	1985-10-15	1987-04-22	Nec Corp	半導体集積回路装置
JP2685756B2 (ja) *	1987-07-20	1997-12-03	株式会社東芝	半導体集積回路装置の設計方法
JPH04340252A (ja) *	1990-07-27	1992-11-26	Mitsubishi Electric Corp	半導体集積回路装置及びセルの配置配線方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US3808475A (en) *	1972-07-10	1974-04-30	Amdahl Corp	Lsi chip construction and method
CA1024661A (fr) *	1974-06-26	1978-01-17	International Business Machines Corporation	Arrangement cablable de pastilles sur circuit integre planaire
US4006492A (en) *	1975-06-23	1977-02-01	International Business Machines Corporation	High density semiconductor chip organization
CA1091360A (fr) *	1975-12-29	1980-12-09	Takao Uehara	Dispositifs d'interconnexion normalises

1978
- 1978-06-14 CA CA305,463A patent/CA1102009A/fr not_active Expired
- 1978-07-25 JP JP9006178A patent/JPS5441088A/ja active Pending
- 1978-08-16 EP EP78100654A patent/EP0001209A1/fr not_active Withdrawn
- 1978-08-25 IT IT27013/78A patent/IT1110167B/it active
1979
- 1979-07-17 US US06/058,360 patent/UST100501I4/en active Pending

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4623911A (en)	1983-12-16	1986-11-18	Rca Corporation	High circuit density ICs
US4748494A (en)	1985-04-19	1988-05-31	Hitachi, Ltd.	Lead arrangement for reducing voltage variation
US10878158B2 (en) *	2018-07-16	2020-12-29	Taiwan Semiconductor Manufacturing Company, Ltd.	Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same
US11409937B2 (en)	2018-07-16	2022-08-09	Taiwan Semiconductor Manufacturing Company, Ltd.	Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same
US11797746B2 (en)	2018-07-16	2023-10-24	Taiwan Semiconductor Manufacturing Company, Ltd.	Method of forming semiconductor device having more similar cell densities in alternating rows
US12086524B2 (en)	2018-07-16	2024-09-10	Taiwan Semiconductor Manufacturing Company, Ltd.	Semiconductor device having more similar cell densities in alternating rows

Also Published As

Publication number	Publication date
JPS5441088A (en)	1979-03-31
IT7827013A0 (it)	1978-08-25
CA1102009A (fr)	1981-05-26
IT1110167B (it)	1985-12-23
EP0001209A1 (fr)	1979-04-04

Publication	Publication Date	Title
US4624045A (en)	1986-11-25	Method of making thin film device
UST100501I4 (en)	1981-04-07	Integrated circuit layout utilizing separated active circuit and wiring regions
JPS5756958A (en)	1982-04-05	Semiconductor device
GB1513116A (en)	1978-06-07	Formation of integrated circuits
JPS55154762A (en)	1980-12-02	Semiconductor memory
US3457631A (en)	1969-07-29	Method of making a high frequency transistor structure
JPS5283070A (en)	1977-07-11	Production of semiconductor device
JPS6257259B2 (fr)	1987-11-30
JPS5231627A (en)	1977-03-10	Semiconductor memory unit
KR950004415A (ko)	1995-02-18	반도체 장치 및 그 제조방법
JPS57202776A (en)	1982-12-11	Semiconductor device
KR900019222A (ko)	1990-12-24	필드플레이트를 갖춘 반도체장치 및 그 제조방법
TW344130B (en)	1998-11-01	Termination structure for semiconductor device and process for its manufacture
JPS5730390A (en)	1982-02-18	Josephson junction element
KR950013902B1 (ko)	1995-11-17	반도체 메모리장치 및 그 제조방법
JPH0265271A (ja)	1990-03-05	ダイナミック型メモリ
KR960043301A (ko)	1996-12-23	불휘발성 메모리 장치 및 그 제조방법
JPH0475665B2 (fr)	1992-12-01
JPS55130145A (en)	1980-10-08	Semiconductor integrated circuit device
KR970072416A (ko)	1997-11-07	반도체 기억장치의 셀 커패시터 제조방법
JPS5658279A (en)	1981-05-21	Panel for solar cell
JPS5756959A (en)	1982-04-05	Semiconductor device and manufacture thereof
JPS5654078A (en)	1981-05-13	Solar battery
JPS5335472A (en)	1978-04-01	Production of semiconductor unit
JPS5627971A (en)	1981-03-18	Semiconductor device and manufacture thereof