WO2002103797A3 - Circuit integre de type cmos a tenue en tension elevee - Google Patents

Circuit integre de type cmos a tenue en tension elevee Download PDF

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Publication number
WO2002103797A3
WO2002103797A3 PCT/FR2002/002063 FR0202063W WO02103797A3 WO 2002103797 A3 WO2002103797 A3 WO 2002103797A3 FR 0202063 W FR0202063 W FR 0202063W WO 02103797 A3 WO02103797 A3 WO 02103797A3
Authority
WO
WIPO (PCT)
Prior art keywords
casing
type
conductivity
cmos circuit
integrated cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/FR2002/002063
Other languages
English (en)
Other versions
WO2002103797A2 (fr
Inventor
Rosalia Germana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to JP2003506008A priority Critical patent/JP2004531073A/ja
Priority to EP02762491A priority patent/EP1396025A2/fr
Priority to US10/480,911 priority patent/US7012309B2/en
Publication of WO2002103797A2 publication Critical patent/WO2002103797A2/fr
Publication of WO2002103797A3 publication Critical patent/WO2002103797A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

L'invention concerne un circuit integre de type CMOS comprenant, dans un substrat semiconducteur (1) d'un premier type de conductivite, un caisson (2) du deuxieme type de conduc- tivite a dopage retrograde, la limite dudit caisson etant recou- verte d'une zone isolante inter-caisson (4), les composants contenus dans ledit caisson etant separes entre eux par des zones isolantes intra-caisson (6, 7), des premieres ∩lantations d'isolement (15) a niveau de dopage eleve du deuxieme type de conductivite s'etendant sous chaque zone isolante intra-caisson. Une deuxieme region (21) a niveau de dopage eleve du deuxieme type de conductivite, identique aux premieres regions, s'etend partiellement sous l'isolant inter-caisson au-dela de la peri- pherie de chaque caisson.
PCT/FR2002/002063 2001-06-15 2002-06-14 Circuit integre de type cmos a tenue en tension elevee Ceased WO2002103797A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2003506008A JP2004531073A (ja) 2001-06-15 2002-06-14 高電圧ｃｍｏｓ集積回路
EP02762491A EP1396025A2 (fr) 2001-06-15 2002-06-14 Circuit integre de type cmos a tenue en tension elevee
US10/480,911 US7012309B2 (en) 2001-06-15 2002-06-14 High-voltage integrated CMOS circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR01/07871 2001-06-15
FR0107871A FR2826182A1 (fr) 2001-06-15 2001-06-15 Circuit integre de type cmos a tenue en tension elevee

Publications (2)

Publication Number Publication Date
WO2002103797A2 WO2002103797A2 (fr) 2002-12-27
WO2002103797A3 true WO2002103797A3 (fr) 2003-03-13

Family

ID=8864367

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2002/002063 Ceased WO2002103797A2 (fr) 2001-06-15 2002-06-14 Circuit integre de type cmos a tenue en tension elevee

Country Status (5)

Country Link
US (1) US7012309B2 (fr)
EP (1) EP1396025A2 (fr)
JP (1) JP2004531073A (fr)
FR (1) FR2826182A1 (fr)
WO (1) WO2002103797A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101331612B (zh) * 2005-12-19 2012-12-19 Nxp股份有限公司 集成高压二极管及制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57107068A (en) * 1980-12-25 1982-07-03 Fujitsu Ltd Complementary mis semiconductor device
JPS60260144A (ja) * 1984-06-06 1985-12-23 Sony Corp 半導体装置
US4761384A (en) * 1986-06-10 1988-08-02 Siemens Aktiengesellschaft Forming retrograde twin wells by outdiffusion of impurity ions in epitaxial layer followed by CMOS device processing
JPH01308067A (ja) * 1988-06-06 1989-12-12 Nec Corp 半導体装置
JPH0468564A (ja) * 1990-07-10 1992-03-04 Sony Corp 半導体装置の製法
US5631178A (en) * 1995-01-31 1997-05-20 Motorola, Inc. Method for forming a stable semiconductor device having an arsenic doped ROM portion

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5206535A (en) * 1988-03-24 1993-04-27 Seiko Epson Corporation Semiconductor device structure
JPH07176701A (ja) * 1993-12-17 1995-07-14 Nec Corp 半導体装置とその製造方法
JP2000091443A (ja) * 1998-09-14 2000-03-31 Mitsubishi Electric Corp 半導体装置およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57107068A (en) * 1980-12-25 1982-07-03 Fujitsu Ltd Complementary mis semiconductor device
JPS60260144A (ja) * 1984-06-06 1985-12-23 Sony Corp 半導体装置
US4761384A (en) * 1986-06-10 1988-08-02 Siemens Aktiengesellschaft Forming retrograde twin wells by outdiffusion of impurity ions in epitaxial layer followed by CMOS device processing
JPH01308067A (ja) * 1988-06-06 1989-12-12 Nec Corp 半導体装置
JPH0468564A (ja) * 1990-07-10 1992-03-04 Sony Corp 半導体装置の製法
US5631178A (en) * 1995-01-31 1997-05-20 Motorola, Inc. Method for forming a stable semiconductor device having an arsenic doped ROM portion

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 006, no. 200 (E - 135) 9 October 1982 (1982-10-09) *
PATENT ABSTRACTS OF JAPAN vol. 010, no. 129 (E - 403) 14 May 1986 (1986-05-14) *
PATENT ABSTRACTS OF JAPAN vol. 014, no. 105 (E - 0895) 26 February 1990 (1990-02-26) *
PATENT ABSTRACTS OF JAPAN vol. 016, no. 279 (E - 1220) 22 June 1992 (1992-06-22) *

Also Published As

Publication number Publication date
FR2826182A1 (fr) 2002-12-20
US20040183138A1 (en) 2004-09-23
EP1396025A2 (fr) 2004-03-10
US7012309B2 (en) 2006-03-14
JP2004531073A (ja) 2004-10-07
WO2002103797A2 (fr) 2002-12-27

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