WO2004015745A3 - Dispositif mos a double diffusion a tension de seuil programmable - Google Patents

Dispositif mos a double diffusion a tension de seuil programmable Download PDF

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Publication number
WO2004015745A3
WO2004015745A3 PCT/US2003/025108 US0325108W WO2004015745A3 WO 2004015745 A3 WO2004015745 A3 WO 2004015745A3 US 0325108 W US0325108 W US 0325108W WO 2004015745 A3 WO2004015745 A3 WO 2004015745A3
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
threshold voltage
floating gate
dmos device
programmable threshold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/025108
Other languages
English (en)
Other versions
WO2004015745A2 (fr
Inventor
Richard A Blanchard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Semiconductor Inc
Original Assignee
General Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/217,893 external-priority patent/US6882573B2/en
Priority claimed from US10/218,010 external-priority patent/US6734495B2/en
Application filed by General Semiconductor Inc filed Critical General Semiconductor Inc
Priority to JP2004528026A priority Critical patent/JP2005536048A/ja
Priority to EP03751848A priority patent/EP1550150A4/fr
Priority to AU2003269956A priority patent/AU2003269956A1/en
Priority to CN038241536A priority patent/CN1692449B/zh
Publication of WO2004015745A2 publication Critical patent/WO2004015745A2/fr
Publication of WO2004015745A3 publication Critical patent/WO2004015745A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/683—Floating-gate IGFETs having only two programming levels programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures

Landscapes

  • Non-Volatile Memory (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne un dispositif MOS à double diffusion équipé d'une grille flottante possédant une première et une seconde électrode à proximité immédiate de celle-ci. La grille flottante est séparée d'une des première et seconde électrodes par une couche fine de matériau diélectrique dont les dimensions et la composition permettent à des porteurs de charge de traverser par effet de tunnel la couche diélectrique soit en direction de la grille flottante soit à partir de celle-ci. Le phénomène de pénétration par effet tunnel peut être utilisé en vue de créer une tension de seuil pouvant être réglée en vue de fournir un courant précis par placement d'une tension entre une électrode de programmation et le corps/la source et l'électrode de grille du dispositif.
PCT/US2003/025108 2002-08-13 2003-08-11 Dispositif mos a double diffusion a tension de seuil programmable Ceased WO2004015745A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2004528026A JP2005536048A (ja) 2002-08-13 2003-08-11 プログラム可能なしきい値電圧を有するｄｍｏｓ装置
EP03751848A EP1550150A4 (fr) 2002-08-13 2003-08-11 Dispositif mos a double diffusion a tension de seuil programmable
AU2003269956A AU2003269956A1 (en) 2002-08-13 2003-08-11 A dmos device with a programmable threshold voltage
CN038241536A CN1692449B (zh) 2002-08-13 2003-08-11 具有可编程阈值电压的dmos器件

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/218,010 2002-08-13
US10/217,893 US6882573B2 (en) 2002-08-13 2002-08-13 DMOS device with a programmable threshold voltage
US10/217,893 2002-08-13
US10/218,010 US6734495B2 (en) 2002-08-13 2002-08-13 Two terminal programmable MOS-gated current source

Publications (2)

Publication Number Publication Date
WO2004015745A2 WO2004015745A2 (fr) 2004-02-19
WO2004015745A3 true WO2004015745A3 (fr) 2004-04-29

Family

ID=31720179

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/025108 Ceased WO2004015745A2 (fr) 2002-08-13 2003-08-11 Dispositif mos a double diffusion a tension de seuil programmable

Country Status (6)

Country Link
EP (1) EP1550150A4 (fr)
JP (1) JP2005536048A (fr)
KR (1) KR20050056200A (fr)
AU (1) AU2003269956A1 (fr)
TW (1) TWI320232B (fr)
WO (1) WO2004015745A2 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100881015B1 (ko) * 2006-11-30 2009-01-30 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
JP5272472B2 (ja) * 2008-03-28 2013-08-28 サンケン電気株式会社 半導体装置
CN112864234B (zh) * 2019-11-27 2022-04-15 苏州东微半导体股份有限公司 Igbt功率器件
CN112885900B (zh) * 2019-11-29 2022-04-15 苏州东微半导体股份有限公司 一种igbt器件
CN112885827B (zh) * 2019-11-29 2022-04-15 苏州东微半导体股份有限公司 一种半导体超结功率器件
CN117637854B (zh) * 2024-01-24 2024-04-19 苏州华太电子技术股份有限公司 垂直型电容耦合栅控结型场效应晶体管及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5910925A (en) * 1992-01-14 1999-06-08 Sandisk Corporation EEPROM with split gate source side injection
US5963480A (en) * 1988-06-08 1999-10-05 Harari; Eliyahou Highly compact EPROM and flash EEPROM devices

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3007892C2 (de) * 1980-03-01 1982-06-09 Deutsche Itt Industries Gmbh, 7800 Freiburg Floating-Gate-Speicherzelle
EP0205637A1 (fr) * 1985-06-25 1986-12-30 Eaton Corporation Transistor à effet de champ de puissance bidirectionnel à piégeage de charges
JPS6129177A (ja) * 1984-07-19 1986-02-10 Seiko Instr & Electronics Ltd 半導体不揮発性メモリ
US4589009A (en) * 1984-10-09 1986-05-13 The United States Of America As Represented By The Secretary Of The Army Non-volatile piezoelectric memory transistor
JP2654384B2 (ja) * 1987-09-18 1997-09-17 株式会社日立製作所 不揮発性メモリ付大電力半導体装置
JPH022177A (ja) * 1988-06-14 1990-01-08 Sharp Corp 浮遊ゲート付電界効果型トランジスタ
JP3367255B2 (ja) * 1995-03-08 2003-01-14 株式会社デンソー 半導体装置及びその製造方法
US5633518A (en) * 1995-07-28 1997-05-27 Zycad Corporation Nonvolatile reprogrammable interconnect cell with FN tunneling and programming method thereof
JP3371708B2 (ja) * 1996-08-22 2003-01-27 ソニー株式会社 縦型電界効果トランジスタの製造方法
DE69832019T2 (de) * 1997-09-09 2006-07-20 Interuniversitair Micro-Electronica Centrum Vzw Verfahren zur Löschung und Programmierung eines Speichers in Kleinspannungs-Anwendungen und Anwendungen mit geringer Leistung
JP2000232171A (ja) * 1999-02-10 2000-08-22 Nec Kyushu Ltd 半導体装置およびその製造方法
JP2001035942A (ja) * 1999-07-22 2001-02-09 Toyota Central Res & Dev Lab Inc 不揮発性半導体メモリ装置
DE19941684B4 (de) * 1999-09-01 2004-08-26 Infineon Technologies Ag Halbleiterbauelement als Verzögerungselement
JP4277381B2 (ja) * 1999-09-21 2009-06-10 株式会社デンソー 炭化珪素半導体装置及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5963480A (en) * 1988-06-08 1999-10-05 Harari; Eliyahou Highly compact EPROM and flash EEPROM devices
US5910925A (en) * 1992-01-14 1999-06-08 Sandisk Corporation EEPROM with split gate source side injection
US5910915A (en) * 1992-01-14 1999-06-08 Sandisk Corporation EEPROM with split gate source side injection

Also Published As

Publication number Publication date
EP1550150A2 (fr) 2005-07-06
WO2004015745A2 (fr) 2004-02-19
AU2003269956A1 (en) 2004-02-25
TWI320232B (en) 2010-02-01
JP2005536048A (ja) 2005-11-24
AU2003269956A8 (en) 2004-02-25
EP1550150A4 (fr) 2009-08-19
TW200405571A (en) 2004-04-01
KR20050056200A (ko) 2005-06-14

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