WO2004032183A3 - Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur. - Google Patents

Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur. Download PDF

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Publication number
WO2004032183A3
WO2004032183A3 PCT/FR2003/050077 FR0350077W WO2004032183A3 WO 2004032183 A3 WO2004032183 A3 WO 2004032183A3 FR 0350077 W FR0350077 W FR 0350077W WO 2004032183 A3 WO2004032183 A3 WO 2004032183A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
layer
thin film
making
detachable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/FR2003/050077
Other languages
English (en)
Other versions
WO2004032183A2 (fr
Inventor
Chrystelle Lagahe
Bernard Aspar
Aurelie Beaumont
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0212443A external-priority patent/FR2845517B1/fr
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to US10/530,640 priority Critical patent/US7238598B2/en
Priority to AT03780289T priority patent/ATE539446T1/de
Priority to JP2005500039A priority patent/JP4777774B2/ja
Priority to EP03780289A priority patent/EP1550158B1/fr
Publication of WO2004032183A2 publication Critical patent/WO2004032183A2/fr
Publication of WO2004032183A3 publication Critical patent/WO2004032183A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Abstract

L'invention concerne un Procédé de réalisation d'un substrat semiconducteur démontable, comprenant les étapes suivantes : - introduction d'espèces gazeuses dans le substrat (1) selon des conditions permettant la constitution d'une couche fragilisée par la présence dans cette couche de micro-cavités et/ou de micro­ bulles, une couche mince de matériau semiconducteur étant ainsi délimitée entre la couche fragilisée et une face (2) du substrat, - traitement thermique du substrat pour augmenter le niveau de fragilisation de la couche fragilisée, ce traitement thermique étant mené jusqu'à l'apparition de déformations locales de ladite face (2) du substrat (1) sous forme de cloques mais sans générer d'exfoliations de la couche mince lors de cette étape et au cours de la suite du procédé, - épitaxie de matériau semiconducteur (6) sur ladite face du substrat pour fournir au moins une couche épitaxiée sur ladite couche mince.
PCT/FR2003/050077 2002-10-07 2003-10-03 Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur. Ceased WO2004032183A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US10/530,640 US7238598B2 (en) 2002-10-07 2003-10-03 Formation of a semiconductor substrate that may be dismantled and obtaining a semiconductor element
AT03780289T ATE539446T1 (de) 2002-10-07 2003-10-03 Herstellung von einem abnehmbaren halbleitersubstrat und einem halbleiterelement
JP2005500039A JP4777774B2 (ja) 2002-10-07 2003-10-03 剥離可能な半導体基板を形成するための方法ならびに半導体素子を得るための方法
EP03780289A EP1550158B1 (fr) 2002-10-07 2003-10-03 Realisation d un substrat semiconducteur demontable et obten tion d un element semiconducteur.

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR02/12443 2002-10-07
FR0212443A FR2845517B1 (fr) 2002-10-07 2002-10-07 Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur
FR0350130A FR2845518B1 (fr) 2002-10-07 2003-04-25 Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur
FR03/50130 2003-04-25

Publications (2)

Publication Number Publication Date
WO2004032183A2 WO2004032183A2 (fr) 2004-04-15
WO2004032183A3 true WO2004032183A3 (fr) 2004-07-29

Family

ID=32031847

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2003/050077 Ceased WO2004032183A2 (fr) 2002-10-07 2003-10-03 Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur.

Country Status (6)

Country Link
US (1) US7238598B2 (fr)
EP (1) EP1550158B1 (fr)
JP (1) JP4777774B2 (fr)
AT (1) ATE539446T1 (fr)
FR (1) FR2845518B1 (fr)
WO (1) WO2004032183A2 (fr)

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JP4277481B2 (ja) * 2002-05-08 2009-06-10 日本電気株式会社 半導体基板の製造方法、半導体装置の製造方法
JP2006270000A (ja) * 2005-03-25 2006-10-05 Sumco Corp 歪Ｓｉ−ＳＯＩ基板の製造方法および該方法により製造された歪Ｓｉ−ＳＯＩ基板
FR2898431B1 (fr) * 2006-03-13 2008-07-25 Soitec Silicon On Insulator Procede de fabrication de film mince
FR2913968B1 (fr) * 2007-03-23 2009-06-12 Soitec Silicon On Insulator Procede de realisation de membranes autoportees.
US7856212B2 (en) * 2007-08-07 2010-12-21 Intel Corporation Millimeter-wave phase-locked loop with injection-locked frequency divider using quarter-wavelength transmission line and method of calibration
US7977221B2 (en) * 2007-10-05 2011-07-12 Sumco Corporation Method for producing strained Si-SOI substrate and strained Si-SOI substrate produced by the same
US20090124038A1 (en) * 2007-11-14 2009-05-14 Mark Ewing Tuttle Imager device, camera, and method of manufacturing a back side illuminated imager
US20090212397A1 (en) * 2008-02-22 2009-08-27 Mark Ewing Tuttle Ultrathin integrated circuit and method of manufacturing an ultrathin integrated circuit
JP5347345B2 (ja) * 2008-06-16 2013-11-20 旭硝子株式会社 導電性マイエナイト型化合物の製造方法
US20100102419A1 (en) * 2008-10-28 2010-04-29 Eric Ting-Shan Pan Epitaxy-Level Packaging (ELP) System
WO2010062659A1 (fr) * 2008-10-28 2010-06-03 Athenaeum, Llc Système et procédé pour l'assemblage d’un film épitaxial
US7905197B2 (en) * 2008-10-28 2011-03-15 Athenaeum, Llc Apparatus for making epitaxial film
US7967936B2 (en) * 2008-12-15 2011-06-28 Twin Creeks Technologies, Inc. Methods of transferring a lamina to a receiver element
US7927975B2 (en) * 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
KR101963421B1 (ko) * 2011-04-11 2019-03-28 엔디에스유 리서치 파운데이션 별개의 구성요소의 선택적인 레이저 보조 전사
US9023729B2 (en) * 2011-12-23 2015-05-05 Athenaeum, Llc Epitaxy level packaging
US9184094B1 (en) * 2012-01-26 2015-11-10 Skorpios Technologies, Inc. Method and system for forming a membrane over a cavity
US9481566B2 (en) 2012-07-31 2016-11-01 Soitec Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices
JP6757953B2 (ja) * 2016-08-09 2020-09-23 学校法人 名古屋電気学園 表面加工方法、構造体の製造方法
CN106896410B (zh) * 2017-03-09 2019-08-23 成都理工大学 利用声波测井资料解释岩石的变形模量和脆性指数的方法
FR3073083B1 (fr) 2017-10-31 2019-10-11 Soitec Procede de fabrication d'un film sur un feuillet flexible
FR3073082B1 (fr) * 2017-10-31 2019-10-11 Soitec Procede de fabrication d'un film sur un support presentant une surface non plane
FR3094559B1 (fr) 2019-03-29 2024-06-21 Soitec Silicon On Insulator Procédé de transfert de paves d’un substrat donneur sur un substrat receveur

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2748851A1 (fr) * 1996-05-15 1997-11-21 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
US5877070A (en) * 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
EP0961312A2 (fr) * 1998-05-15 1999-12-01 Canon Kabushiki Kaisha Substrat du type SOI fabriqué par collage
FR2797347A1 (fr) * 1999-08-04 2001-02-09 Commissariat Energie Atomique Procede de transfert d'une couche mince comportant une etape de surfragililisation
FR2809867A1 (fr) * 2000-05-30 2001-12-07 Commissariat Energie Atomique Substrat fragilise et procede de fabrication d'un tel substrat
WO2002005344A1 (fr) * 2000-07-12 2002-01-17 Commissariat A L'energie Atomique Procede de decoupage d'un bloc de materiau et de formation d'un film mince

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JP3412470B2 (ja) * 1997-09-04 2003-06-03 三菱住友シリコン株式会社 Ｓｏｉ基板の製造方法
EP0926709A3 (fr) * 1997-12-26 2000-08-30 Canon Kabushiki Kaisha Méthode de fabrication d'une structure SOI
JPH11233449A (ja) * 1998-02-13 1999-08-27 Denso Corp 半導体基板の製造方法
US6291326B1 (en) * 1998-06-23 2001-09-18 Silicon Genesis Corporation Pre-semiconductor process implant and post-process film separation
FR2784795B1 (fr) * 1998-10-16 2000-12-01 Commissariat Energie Atomique Structure comportant une couche mince de materiau composee de zones conductrices et de zones isolantes et procede de fabrication d'une telle structure
US6255195B1 (en) * 1999-02-22 2001-07-03 Intersil Corporation Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method
US6323108B1 (en) * 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
JP4450126B2 (ja) * 2000-01-21 2010-04-14 日新電機株式会社 シリコン系結晶薄膜の形成方法
TW452866B (en) * 2000-02-25 2001-09-01 Lee Tien Hsi Manufacturing method of thin film on a substrate
FR2816445B1 (fr) * 2000-11-06 2003-07-25 Commissariat Energie Atomique Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible
US20020187619A1 (en) * 2001-05-04 2002-12-12 International Business Machines Corporation Gettering process for bonded SOI wafers

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2748851A1 (fr) * 1996-05-15 1997-11-21 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
US5877070A (en) * 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
EP0961312A2 (fr) * 1998-05-15 1999-12-01 Canon Kabushiki Kaisha Substrat du type SOI fabriqué par collage
FR2797347A1 (fr) * 1999-08-04 2001-02-09 Commissariat Energie Atomique Procede de transfert d'une couche mince comportant une etape de surfragililisation
FR2809867A1 (fr) * 2000-05-30 2001-12-07 Commissariat Energie Atomique Substrat fragilise et procede de fabrication d'un tel substrat
WO2002005344A1 (fr) * 2000-07-12 2002-01-17 Commissariat A L'energie Atomique Procede de decoupage d'un bloc de materiau et de formation d'un film mince

Also Published As

Publication number Publication date
US7238598B2 (en) 2007-07-03
JP2006502593A (ja) 2006-01-19
ATE539446T1 (de) 2012-01-15
FR2845518A1 (fr) 2004-04-09
WO2004032183A2 (fr) 2004-04-15
US20060019476A1 (en) 2006-01-26
FR2845518B1 (fr) 2005-10-14
JP4777774B2 (ja) 2011-09-21
EP1550158B1 (fr) 2011-12-28
EP1550158A2 (fr) 2005-07-06

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