WO2005013338A3 - Realisation d’une structure comprenant une couche protegeant contre des traitements chimiques - Google Patents

Realisation d’une structure comprenant une couche protegeant contre des traitements chimiques Download PDF

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Publication number
WO2005013338A3
WO2005013338A3 PCT/FR2004/002040 FR2004002040W WO2005013338A3 WO 2005013338 A3 WO2005013338 A3 WO 2005013338A3 FR 2004002040 W FR2004002040 W FR 2004002040W WO 2005013338 A3 WO2005013338 A3 WO 2005013338A3
Authority
WO
WIPO (PCT)
Prior art keywords
buried layer
protective layer
production
chemical treatment
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/FR2004/002040
Other languages
English (en)
Other versions
WO2005013338A2 (fr
Inventor
Bruno Ghyselen
Olivier Rayssac
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to JP2006521625A priority Critical patent/JP2007500436A/ja
Priority to EP04767815A priority patent/EP1649509A2/fr
Publication of WO2005013338A2 publication Critical patent/WO2005013338A2/fr
Publication of WO2005013338A3 publication Critical patent/WO2005013338A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1924—Preparing SOI wafers with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Element Separation (AREA)
  • Weting (AREA)
  • Photovoltaic Devices (AREA)
  • Led Devices (AREA)

Abstract

Procédé de réalisation d'une structure à plusieurs couches destinée à l'électronique, l'optique ou l'optoélectronique comprenant une couche enterrée. Le procédé comprend les étapes successives suivantes : a) formation de couches de la structure, comprenant la formation de la couche enterrée ; b) traitement chimique de la structure employant des espèces chimiques aptes à graver sensiblement le matériau constituant la couche enterrée. L'étape a) comprend la formation sur la couche enterrée d'une couche de protection, elle aussi enterrée, en un matériau choisi pour résister suffisamment à l'attaque chimique d'espèces chimiques du traitement mis en œuvre lors de l'étape b), condamnant ainsi des accès possibles à la couche enterrée par lesquels ces espèces pourraient s'infiltrer. L'invention concerne en outre une application du procédé à la réalisation de structures destinées à l'électronique, l'optique ou l'optoélectronique.
PCT/FR2004/002040 2003-07-30 2004-07-29 Realisation d’une structure comprenant une couche protegeant contre des traitements chimiques Ceased WO2005013338A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006521625A JP2007500436A (ja) 2003-07-30 2004-07-29 耐化学処理保護層を有する積層構造体の製造法
EP04767815A EP1649509A2 (fr) 2003-07-30 2004-07-29 Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0309380 2003-07-30
FR0309380A FR2858461B1 (fr) 2003-07-30 2003-07-30 Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques

Publications (2)

Publication Number Publication Date
WO2005013338A2 WO2005013338A2 (fr) 2005-02-10
WO2005013338A3 true WO2005013338A3 (fr) 2005-06-30

Family

ID=34043671

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2004/002040 Ceased WO2005013338A2 (fr) 2003-07-30 2004-07-29 Realisation d’une structure comprenant une couche protegeant contre des traitements chimiques

Country Status (7)

Country Link
US (1) US7169683B2 (fr)
EP (1) EP1649509A2 (fr)
JP (1) JP2007500436A (fr)
KR (1) KR100751619B1 (fr)
CN (1) CN100401499C (fr)
FR (1) FR2858461B1 (fr)
WO (1) WO2005013338A2 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7235461B2 (en) * 2003-04-29 2007-06-26 S.O.I.Tec Silicon On Insulator Technologies Method for bonding semiconductor structures together
FR2858461B1 (fr) * 2003-07-30 2005-11-04 Soitec Silicon On Insulator Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques
ATE441206T1 (de) * 2004-12-28 2009-09-15 Soitec Silicon On Insulator Verfahren zum erhalten einer dünnen schicht mit einer geringen dichte von líchern
CN101529578B (zh) * 2006-10-27 2012-01-11 硅绝缘体技术有限公司 用于转移在具有空位团的基片中形成的薄层的改进方法
US7678668B2 (en) * 2007-07-04 2010-03-16 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device
FR2926672B1 (fr) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication de couches de materiau epitaxie
RU2368034C1 (ru) * 2008-05-13 2009-09-20 Институт физики полупроводников Сибирского отделения Российской академии наук Способ изготовления структуры кремний на изоляторе
US20110180896A1 (en) * 2010-01-25 2011-07-28 International Business Machines Corporation Method of producing bonded wafer structure with buried oxide/nitride layers
JP6248458B2 (ja) * 2013-08-05 2017-12-20 株式会社Sumco 貼り合わせウェーハの製造方法および貼り合わせウェーハ
FR3042649B1 (fr) * 2015-10-20 2019-06-21 Soitec Procede de fabrication d'une structure hybride
FR3074608B1 (fr) * 2017-12-05 2019-12-06 Soitec Procede de preparation d'un residu de substrat donneur, substrat obtenu a l'issu de ce procede, et utilisation d'un tel susbtrat

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4771016A (en) * 1987-04-24 1988-09-13 Harris Corporation Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor
US5517047A (en) * 1992-07-28 1996-05-14 Harris Corporation Bonded wafer processing
US6313012B1 (en) * 1993-09-06 2001-11-06 Hitachi, Ltd. Method of fabricating multi-layered structure having single crystalline semiconductor film formed on insulator
US20020070454A1 (en) * 2000-11-30 2002-06-13 Seiko Epson Corporation SOI substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the SOI substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus
US6410938B1 (en) * 2001-04-03 2002-06-25 Advanced Micro Devices, Inc. Semiconductor-on-insulator device with nitrided buried oxide and method of fabricating
FR2823599A1 (fr) * 2001-04-13 2002-10-18 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
FR2835095A1 (fr) * 2002-01-22 2003-07-25 Soitec Silicon On Insulator Procede de preparation d'ensembles a semi-conducteurs separables, notamment pour former des substrats pour l'electronique, l'optoelectrique et l'optique
FR2835096A1 (fr) * 2002-01-22 2003-07-25 Soitec Silicon On Insulator Procede de fabrication d'un substrat auto-porte en materiau semi-conducteur monocristallin

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Publication number Priority date Publication date Assignee Title
JP3214631B2 (ja) * 1992-01-31 2001-10-02 キヤノン株式会社 半導体基体及びその作製方法
US5882532A (en) * 1996-05-31 1999-03-16 Hewlett-Packard Company Fabrication of single-crystal silicon structures using sacrificial-layer wafer bonding
SG67458A1 (en) * 1996-12-18 1999-09-21 Canon Kk Process for producing semiconductor article
JPH11111839A (ja) * 1997-10-01 1999-04-23 Denso Corp 半導体基板およびその製造方法
JP3358550B2 (ja) * 1998-07-07 2002-12-24 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JP3887973B2 (ja) * 1998-10-16 2007-02-28 信越半導体株式会社 Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
JP3537690B2 (ja) * 1998-12-25 2004-06-14 京セラ株式会社 化合物半導体装置およびその製造法
JP2000315727A (ja) * 1999-03-02 2000-11-14 Rohm Co Ltd 半導体装置の製造方法
US6902987B1 (en) * 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6902656B2 (en) * 2002-05-24 2005-06-07 Dalsa Semiconductor Inc. Fabrication of microstructures with vacuum-sealed cavity
US6979630B2 (en) * 2002-08-08 2005-12-27 Isonics Corporation Method and apparatus for transferring a thin layer of semiconductor material
FR2858461B1 (fr) * 2003-07-30 2005-11-04 Soitec Silicon On Insulator Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques
FR2866983B1 (fr) * 2004-03-01 2006-05-26 Soitec Silicon On Insulator Realisation d'une entite en materiau semiconducteur sur substrat
FR2867310B1 (fr) * 2004-03-05 2006-05-26 Soitec Silicon On Insulator Technique d'amelioration de la qualite d'une couche mince prelevee
US7087134B2 (en) * 2004-03-31 2006-08-08 Hewlett-Packard Development Company, L.P. System and method for direct-bonding of substrates

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4771016A (en) * 1987-04-24 1988-09-13 Harris Corporation Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor
US5517047A (en) * 1992-07-28 1996-05-14 Harris Corporation Bonded wafer processing
US6313012B1 (en) * 1993-09-06 2001-11-06 Hitachi, Ltd. Method of fabricating multi-layered structure having single crystalline semiconductor film formed on insulator
US20020070454A1 (en) * 2000-11-30 2002-06-13 Seiko Epson Corporation SOI substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the SOI substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus
US6410938B1 (en) * 2001-04-03 2002-06-25 Advanced Micro Devices, Inc. Semiconductor-on-insulator device with nitrided buried oxide and method of fabricating
FR2823599A1 (fr) * 2001-04-13 2002-10-18 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
FR2835095A1 (fr) * 2002-01-22 2003-07-25 Soitec Silicon On Insulator Procede de preparation d'ensembles a semi-conducteurs separables, notamment pour former des substrats pour l'electronique, l'optoelectrique et l'optique
FR2835096A1 (fr) * 2002-01-22 2003-07-25 Soitec Silicon On Insulator Procede de fabrication d'un substrat auto-porte en materiau semi-conducteur monocristallin

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
TATE N ET AL: "Defect reduction of bonded SOI wafers by post anneal process in H2 ambient", SOI CONFERENCE, 1998. PROCEEDINGS., 1998 IEEE INTERNATIONAL STUART, FL, USA 5-8 OCT. 1998, NEW YORK, NY, USA,IEEE, US, 5 October 1998 (1998-10-05), pages 141 - 142, XP010309913, ISBN: 0-7803-4500-2 *

Also Published As

Publication number Publication date
KR100751619B1 (ko) 2007-08-22
EP1649509A2 (fr) 2006-04-26
CN1833315A (zh) 2006-09-13
JP2007500436A (ja) 2007-01-11
FR2858461B1 (fr) 2005-11-04
US20050026391A1 (en) 2005-02-03
FR2858461A1 (fr) 2005-02-04
CN100401499C (zh) 2008-07-09
KR20060033917A (ko) 2006-04-20
US7169683B2 (en) 2007-01-30
WO2005013338A2 (fr) 2005-02-10

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