WO2010143369A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2010143369A1
WO2010143369A1 PCT/JP2010/003580 JP2010003580W WO2010143369A1 WO 2010143369 A1 WO2010143369 A1 WO 2010143369A1 JP 2010003580 W JP2010003580 W JP 2010003580W WO 2010143369 A1 WO2010143369 A1 WO 2010143369A1
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Prior art keywords
bump
semiconductor element
element substrate
film
semiconductor device
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English (en)
Japanese (ja)
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山口欣秀
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01255—Changing the shapes of bumps by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07232—Compression bonding, e.g. thermocompression bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Definitions

  • the present invention relates to a semiconductor device in which semiconductor elements of at least two stages or more are stacked and a manufacturing method thereof, and relates to a bump electrode structure of the semiconductor device and a bump electrode bonding method.
  • the second semiconductor element is stacked on top of the first semiconductor element to construct a so-called three-dimensional structure to realize the shortest connection between the semiconductor elements, thereby trying to maximize the performance of each semiconductor element. Attempts to do so have been proposed.
  • Patent Document 1 in order to connect two upper and lower semiconductor chips at the shortest distance, an interposer chip provided with a through hole is disposed between the upper and lower semiconductor chips, A structure has been proposed in which a protruding electrode provided on the surface of a semiconductor chip is pressed into a through hole.
  • a plurality of semiconductor chips are three-dimensionally stacked to achieve connection with the shortest wiring length.
  • the convex external connection terminal provided on the semiconductor chip arranged on the upper side is pressed and injected into the concave external connection terminal provided on the semiconductor chip arranged on the lower side.
  • a technique of compositionally flowing the metal of the external connection terminal is employed.
  • the vibration width of the bonding tool is required to be a minimum of about plus or minus 10 micrometers.
  • the amplitude width of the bonding tool is less than plus or minus 10 micrometers, the amount of plastic deformation of the metal bumps is reduced, and as a result, the amount of composition flow is also reduced, so that a sufficient connection cross-sectional area is obtained at the contact portion between the external connection terminals. This is because it is difficult to ensure the above.
  • the position displacement of the metal bumps is generated by about 10 micrometers, and such bump displacement reduces the position accuracy of the bonding.
  • Patent Document 1 since a through hole is provided in a chip, a large pressing load is applied to a semiconductor chip having a hole (usually made of a brittle material such as silicon). It cannot be denied that there is a risk that the chip will brittlely break. In addition, it is not preferable to apply an excessive pressing load in a brittle material processing step even for a semiconductor chip having no holes.
  • compound semiconductors other than silicon for example, semiconductor chips with low brittle fracture resistance such as SiC and GaN, needless to say, it is highly necessary to avoid an excessive pressing load from the viewpoint of suppressing brittle fracture of the chip.
  • the above Patent Document 1 uses a ball bonding method using Au wires (see Paragraph 0034 of the above Patent Document 1).
  • the tip of the Au wire is melted to form the Au ball part, and then the ultrasonic wave is applied by pressing the ball part against the desired electrode pad location on the chip surface.
  • the bumps are made by a series of processes of thermocompression bonding and cutting the ball tip from the Au wire.
  • Small-sized Au wires for example, small-diameter Au wires having a diameter of 20 micrometers or less, are difficult to handle and are therefore less expensive and therefore expensive.
  • the plating bump method is known as a method for arranging a large number of Au bumps at a full grid and a narrow pitch.
  • Au bumps often have poor adhesion to the underfill material, and as a result, there is a tendency for gaps to form at the interface between the underfill and Au bumps, leading to a decrease in insulation reliability.
  • Patent Document 1 is not necessarily advantageous for application to a three-dimensional stack of semiconductor chips having a large number of bumps.
  • the inventor of the present application has been able to obtain a good result by adopting the following structure, configuration, and means as a result of searching for a technique for improving the technique described in the above publication, and has reached the present invention.
  • one structure / configuration of a semiconductor device is as follows.
  • a convex metallic conductor bump formed on the surface of the first semiconductor element substrate and a convex metallic conductor bump formed on the surface of the second semiconductor element substrate are bonded to each other.
  • the tip of the first convex metallic conductor bump formed on the surface of the first semiconductor element substrate is sharpened in advance.
  • the second convex metallic conductor bump formed on the surface of the second semiconductor element substrate has a composite structure composed of at least three kinds of materials, that is, a top portion, a side wall portion, and a main body portion, and the main body portion is flexible. Metal.
  • the tip portion of the first convex metallic conductor bump having a sharp tip is press-fitted into the soft metal layer that is the main body portion of the second convex metallic conductor bump.
  • the first surface of the semiconductor element substrate has a first bump with a sharp tip
  • the second surface is made of at least three kinds of materials including a top portion, a side wall portion, and a main body portion made of a soft metal.
  • a semiconductor element substrate having a second bump having a composite structure is used.
  • At least three semiconductor element substrates with double-sided bumps having such a structure are prepared, the 1-1st bump having a sharp tip formed in advance on the first surface of the first semiconductor element substrate, A tip formed beforehand on the first surface of the second semiconductor element substrate is bonded to the second surface of the second semiconductor element substrate bonded to the second bump 2-2 containing a soft metal formed in advance.
  • the structure is such that the 2-1 bumps with sharp edges and the 3-2 bumps containing a soft metal formed in advance on the second surface of the third semiconductor element substrate are joined.
  • the present invention also provides a method for manufacturing the semiconductor device according to the present invention.
  • the manufacturing method of the semiconductor device provided by the present invention is as follows.
  • a first metal conductor layer having a uniform thickness is formed on the surface of the first semiconductor element substrate, and a desired portion of the first uniform thickness metal conductor film is selectively processed and removed by a wet etching method.
  • a first semiconductor element substrate with bumps is produced.
  • a method such as photolithography is desirable.
  • a second semiconductor element substrate is prepared separately from the first semiconductor element substrate, and a second metal conductor layer film is formed on the surface with a uniform film thickness.
  • a conductor layer film (third conductor layer, fourth conductor layer) made of various types of conductors, it is selectively removed leaving a desired portion of the second to fourth metal conductor layer films.
  • the method of forming the third conductor layer and the fourth conductor layer may be an etching method or a plating method.
  • the second and second plating layers are formed after the third and fourth conductor layers are continuously formed only at the locations where the plating is selectively deposited using photolithography technology. By removing unnecessary portions of the conductor layer film, desired portions of the second to fourth metal conductor layer films can be left.
  • the first bumped semiconductor element substrate and the second bumped semiconductor element substrate are arranged so that their relative positions are up and down, and the first bumped semiconductor element substrate The bump position of the substrate is matched with the bump position of the second bumped semiconductor element substrate.
  • the first bumped semiconductor element is so pressed that the bump provided on the first bumped semiconductor element substrate is pressed into the bump provided on the second bumped semiconductor element substrate.
  • the substrate and the second bumped semiconductor element substrate are moved relative to each other.
  • the present invention provides a manufacturing method for realizing a chip laminated structure in which at least two semiconductor chips are laminated and joined.
  • thermocompression bonding where multiple semiconductor chips stacked in three dimensions are connected with the shortest wiring length, a bump with a sharp tip is pressed into a soft metal bump. Reliable joining is possible.
  • FIG. 6 is a schematic diagram for explaining a cross-sectional structure in one form of the partial process in the method for manufacturing a semiconductor device according to the example of the present invention.
  • FIG. 10 is a schematic view for explaining a cross-sectional structure in one form of another partial process in the method for manufacturing a semiconductor device according to the example of the present invention.
  • FIG. 10 is a schematic view for explaining a cross-sectional structure in one form of still another partial process in the method for manufacturing a semiconductor device according to the example of the present invention. It is the schematic which shows the cross section of another 1 form of the semiconductor device concerning the Example of this invention.
  • FIG. 1 shows a schematic cross-sectional structure of the semiconductor device of this embodiment.
  • a plurality of convex metal conductor bumps 2 are formed on the surface of the first semiconductor element substrate 1, and a plurality of convex metal conductor bumps 4 are formed on the surface of the second semiconductor element substrate 3. Is formed.
  • the first semiconductor element substrate 1 and the second semiconductor element substrate 3 are arranged with their surfaces facing each other, and the convex metallic conductor bumps 2 provided on the first semiconductor element substrate 1 are second.
  • the convex metallic conductor bumps 4 provided on the semiconductor element substrate 3 are press-fitted to electrically connect the convex metallic conductor bumps 2 and 4 to each other.
  • the gap portion between the first semiconductor element substrate 1 and the second semiconductor element substrate 3 is filled with an underfill material 5 so as to fill the gap between the metallic conductor bumps.
  • the second semiconductor element substrate 3 is fixed so as not to be separated.
  • the underfill material 5 not only fixes the semiconductor element substrate 1 and the second semiconductor element substrate 3, but also ensures insulation reliability between the metallic conductor bumps, and the stress of the underfill material 5 itself. Distributing action contributes to securing connection reliability.
  • the metallic conductor bump 4 provided on the second semiconductor element substrate 3 uses a composite structure made of at least three kinds of materials.
  • a composite structure made of four kinds of materials that is, a height matching layer 4a, a soft metal layer 4b, a top layer 4c, and a side wall portion 4d was used.
  • the height matching layer 4a employed in the present embodiment is a layer for controlling the press-fitting depth when the convex metallic conductor bump 2 is press-fitted into the convex metallic conductor bump 4.
  • the gap between the semiconductor element substrate 1 and the semiconductor element substrate 3 is precisely controlled so as to have a desired value.
  • the numerical variation range can also be controlled. More specifically, the variation range of the gap value between the semiconductor element substrate 1 and the semiconductor element substrate 3 is substantially the same as the thickness variation range of the height matching layer 4a. It is relatively easy to manufacture the thickness variation of the height matching layer 4a so that the average thickness of the height matching layer 4a is equal to or less than 10%.
  • Control of the variation range of the gap value between the substrate 1 and the semiconductor element substrate 3 to plus or minus 10% or less is easily realized.
  • the details of the manufacturing method of the height matching layer 4a will be described later, but if the manufacturing method of the height matching layer 4a is devised, the variation range of the gap value can be further suppressed. More specifically, when the average thickness of the height matching layer 4a is 5 micrometers, the variation range of the gap value between the semiconductor element substrate 1 and the semiconductor element substrate 3 is plus or minus 0.5 micrometers. Control is performed as follows.
  • the height matching layer 4a as described above, precise control of the gap between the semiconductor element substrates is realized, and as a result, the occurrence of defects in the filling process of the underfill material 5 has been successfully reduced. .
  • This is considered to be because the underfill filling conditions that are optimum for the desired gap value can be selected because the gap between the semiconductor element substrates can be precisely controlled.
  • the gap between semiconductor element substrates is one of the main factors of flow path resistance in the filling process of the underfill 5.
  • the height matching layer 4a for precisely controlling the gap between the semiconductor element substrates as in this embodiment.
  • the height matching layer 4a is not provided, the flow resistance in the filling process of the underfill 5 is reduced unless another control method or manufacturing method for stabilizing the value of the gap between the semiconductor element substrates is employed. There is an increased risk of underfill filling problems due to instability.
  • the soft metal layer 4 b is a main body portion of the metal conductor bump 4, and the metal conductor bump 2 is press-fitted to form a bonding interface with the metal conductor bump 2.
  • the metal conductor bump 2 is press-fitted to form a bonding interface with the metal conductor bump 2.
  • a wide variety of materials are known as easily deformable conductors, but the present inventors prefer a metal material or an alloy material rather than a conductive resin from the viewpoint of forming a reliable bonding interface with the metallic conductor bump 2. It was judged.
  • the applicability to the technology of the present invention was examined, and a metallic material having a Brunel hardness of 100 MPa or less is desirable, and a guideline is obtained that the Brunel hardness is particularly preferably less than 50 MPa. It was. On the other hand, if the Brunner hardness is 50 MPa or more, the load required in the process of press-fitting the metallic conductor bump 2 becomes large, which may affect the operating characteristics of the semiconductor element.
  • Sn does not fall within the category of the most preferable conductor metal as the soft metal layer 4b of the present invention because the Brunel hardness is 51 MPa.
  • a bump top layer 4 c is provided on the top of the bump of the metal conductor bump 4, and serves as a film that prevents oxidation of the top of the metal conductor bump 4. Since the bump top layer 4c needs to be broken when the convex metallic conductor bump 2 is press-fitted into the convex metallic conductor bump 4, it is desirable that the bump top layer 4c be a film that can be easily broken. As a result of studying the applicability of the present invention to some materials that can be easily broken, the inventor of the present application press-fits the convex metallic conductor bump 2 if the film has a shear strength of 50 GPa or less.
  • the guideline was obtained that it is difficult to cause an obstacle when the shear strength is 30 GPa or less and the film thickness is 1.0 micrometer or less.
  • a metal thin film is desirable for the bump top layer 4c of the present invention.
  • the thickness is limited to 1.0 ⁇ m or less at the maximum.
  • the bump top layer 4c was fabricated in a thickness range of 0.05 to 0.40 micrometers. This is because if the thickness of the bump top layer 4c is less than 0.05 micrometers, there is a tendency that the effect of preventing the oxidation of the metallic conductor bump 4 cannot be sufficiently obtained. If the bump top layer 4c produced with a film thickness in the range of 0.05 to 0.40 micrometers is used, there will be no particular problem with the rupture when the convex metallic conductor bumps 2 are press-fitted. Further, if the bump top layer 4c is thick, a fractured fragment that becomes a remnant of the bump top layer 4c may be generated near the interface between the metal conductor bump 2 and the metal conductor bump 4.
  • the film thickness is limited in the range of 0.05 to 0.40 micrometers, the generation of breakage fragments that become debris is negligible.
  • a slightly broken piece reacts with In employed as the soft metal layer 4b to form an In—Ag eutectic (eutectic temperature of 141 ° C.) and diffuses into the soft metal layer 4b, so that the bump top layer
  • In—Ag eutectic eutectic temperature of 141 ° C.
  • the bump top layer 4c having an appropriate film thickness (0.05 to 0.40 micrometer)
  • the fragments are the height of the conductor of the bump 2 and the inside of the conductor bump 4.
  • the metal conductor bump 4 further has a side wall portion 4d formed on the side wall portion thereof.
  • the side wall portion 4 d is a layer for ensuring adhesion with the underfill material 5, and may have a minimum thickness that can maintain adhesion with the underfill material 5. Therefore, depending on the material of the metal layer 4b, a natural oxide film that spontaneously forms on the side wall of the soft metal layer 4b may be used instead of actively forming a film.
  • the sidewall portion 4d is an indium oxide film generated by natural oxidation of In used for the soft metal layer 4b. The indium oxide film is quickly formed on the surface of In in the air to form a thin and strong film, and has the effect of chemically stabilizing In.
  • the natural oxide film of In naturally generated as described above as the side wall portion 4d.
  • an Ag thin film that is less ionized than In used in the soft metal layer 4b that is the main body portion of the bump 4 is formed on the bump top layer 4c. The structure facilitates the formation of a natural oxide film of In.
  • the convex metal conductor bumps 2 are press-fitted into the metal conductor bumps 4 made of four kinds of materials, that is, the height matching layer 4a, the soft metal layer 4b, the top layer 4c, and the side wall 4d shown in FIG.
  • An example of a schematic cross-sectional structure in which the state is enlarged is shown in FIG.
  • the convex metallic conductor bumps 2 do not penetrate deeper than they hit the top of the height matching layer 4a.
  • the thickness of the height matching layer 4a is about 50% with respect to the metallic conductor bump 4
  • the thickness of the soft metal layer 4b is about 48% with respect to the entire thickness of the metallic conductor bump 4, and the top layer 4c.
  • the thickness of the convex metallic conductor bump 2 is slightly thicker than that of the soft metal layer 4b, and is about 50% of the thickness of the metallic conductor bump 4 in this embodiment.
  • the thickness of the convex metallic conductor bump 2 should be equal to or greater than the thickness of the soft metal layer 4b, and be in the range of 10 to 95% with respect to the total thickness of the metallic conductor bump 4. Is desirable.
  • the soft metal layer 4b must be thinned as a result. There is a growing concern that the bonding interface between the shape metallic conductor bump 2 and the metallic conductor bump 4 becomes small and the bonding reliability is insufficient. On the contrary, when the thickness of the convex metallic conductor bump 2 exceeds 95% with respect to the entire thickness of the metallic conductor bump 4, the ratio of the soft metal layer 4 b to the entire metallic conductor bump 4 inevitably. Is increased, in other words, the proportion of the height matching layer 4a is decreased, and therefore, the tendency for the gap controllability between the semiconductor element substrate 1 and the semiconductor element substrate 3 to decrease is increased.
  • the convex metallic conductor bump 2 As illustrated in FIG. 3, the convex metallic conductor bump 2 has a pointed tip, and the tip on the small diameter side is a top layer 4 c formed on the surface of the convex metallic conductor bump 4. It penetrates, is press-fitted into the soft metal layer 4b, and is joined in a state of abutting against the height matching layer 4a. On the other hand, the tip on the large-diameter side of the convex metallic conductor bump 2 is connected to the surface of the first semiconductor element substrate, which is omitted in FIG.
  • the tip diameter on the large diameter side of the convex metallic conductor bump 2 is desirable to make the tip diameter on the large diameter side of the convex metallic conductor bump 2 larger than the thickness (height) of the convex metallic conductor bump 2. More specifically, the tip diameter on the large diameter side of the convex metallic conductor bump 2 is desirably about 200% or more with respect to the thickness (height) of the convex metallic conductor bump 2. . This is because, by setting such a diameter / thickness ratio, a simple manufacturing process can be adopted, and the cost can be reduced. In this embodiment, the tip diameter on the large diameter side of the convex metallic conductor bump 2 is 10 micrometers, and the thickness (height) of the convex metallic conductor bump 2 is 4.8 micrometers.
  • the ratio of the diameter of the large-diameter side to the small-diameter side of the convex-shaped metallic conductor bump 2 is a numerical value that represents the sharpness of the tip of the convex-shaped metallic conductor bump 2.
  • the tip of the convex metallic conductor bump 2 is pointed. Since specific specifications are employed in which the film thickness and material of the top layer 4c of the bump 4 and the soft metal layer 4b inside the bump 4 are limited, the tip of the conductor bump 2 does not need to be extremely sharp.
  • the conductor bump 2 of the present embodiment has an axis substantially perpendicular to the semiconductor surface, and an angle 8 formed between the outer surface near the tip and a plane parallel to the semiconductor surface is about 35 to 55 degrees. It is made to be a range. If it is excessively sharp beyond 55 degrees, there is a higher risk of problems such as buckling of the bump tip during the manufacturing process. Conversely, at an obtuse angle of less than 35 degrees, the convex metallic conductor bump 4 There is a tendency that a large load is required in the penetration process of the top layer 4c formed on the surface and the press-fitting process into the soft metal layer 4b.
  • the angle is not limited to the tip but strictly near the tip, and a minute region including the tip of the bump 4 may be a flat shape or a rounded shape parallel to the semiconductor element substrate.
  • the convex metallic conductor bump 2 of the present invention is press-fitted into the soft metal layer 4b inside the convex metallic conductor bump 4 as described above, the material is higher in hardness than the soft metal layer 4b. It is necessary that buckling does not occur in the press-fitting process. From such a viewpoint, in the present invention, it is desirable to select a metal conductor having a shear strength of 25 GPa or more for the convex metallic conductor bump 2. More specifically, Au, Ag, Cu, Ni, NiCu alloy, CuSn alloy (speculum alloy), Ti, and the like.
  • the height matching layer 4a in the convex metallic conductor bump 4 with which the tip of the metallic conductor bump 2 abuts can be easily deformed or buckled due to the abutting of the tip of the metallic conductor bump 2. It is desirable that this does not occur.
  • the material of the height matching layer 4a is preferably selected from a conductor having a Mohs hardness of 0.5 or more higher than that of the metallic conductor bump 2.
  • a nickel film (Mohs hardness 4.0) having a Mohs hardness 1.0 larger than the copper film (Mohs hardness 3.0) is employed.
  • the hardness of the nickel film can be controlled by its manufacturing method, and the height matching layer 4a was produced using a plating method having a wide hardness control range (details of the manufacturing method of the height matching layer 4a will be described later).
  • a method for controlling the film hardness using a plating method is as follows: an additive called a leveler or brightener is added to the plating solution to suppress unevenness on the surface of the plating film so that a smooth surface is obtained. good.
  • an additive called a leveler or brightener is added to the plating solution to suppress unevenness on the surface of the plating film so that a smooth surface is obtained. good.
  • the material of the conductor bump 2, the internal structure of the conductor bump 4, and the material, thickness, hardness, and shape of each constituent layer are finely defined, so that reliable bonding at low temperature and low load can be realized. .
  • more than 1,000 bumps can be bonded together, and when semiconductor chips with low brittle fracture resistance such as SiC and GaN are laminated and bonded according to the specifications of the present embodiment, there is no chip destruction. We were able to join.
  • FIG. 4 is a diagram showing a schematic cross-sectional structure for explaining a manufacturing method for producing the conductor bump 2 on the first semiconductor element substrate 1.
  • FIG. 4A is a schematic diagram showing a cross-sectional structure of the first semiconductor element substrate 1 used in this example. Although the detailed structure is omitted here, at least one semiconductor circuit is formed on the first semiconductor element substrate 1, and the first surface of the first semiconductor element substrate 1 is external to each semiconductor circuit. An output terminal 6 is provided.
  • a first uniform thickness conductor layer 7 is formed with a uniform thickness so as to completely cover the external output terminal 6 (FIG. 4B). Since this figure is only a schematic diagram, the detailed layer structure of the first uniform-thickness conductor layer 7 is not described, but the first uniform-thickness conductor layer 7 is a multilayer film for convenience of the manufacturing process. It does not matter.
  • the uniform-thickness conductor layer 7 employs a two-layer film made of two kinds of materials, Cr and Cu, and in order to ensure film thickness uniformity, both layers are continuously formed using a sputtering method. Filmed.
  • a Cr film having a thickness of 75 nanometers is used in order to ensure that the first semiconductor element substrate 1 and the first uniform thickness conductor layer 7 are in close contact with each other.
  • other materials such as Ti and W are used.
  • an adhesive film may be used instead.
  • the Cu film of the first uniform thickness conductor layer 7 is formed so as to have a thickness of 4.9 micrometers.
  • the first semiconductor element substrate 1 having the conductor bumps 2 is produced by selectively etching away the desired position of the first uniform thickness conductor layer 7 (FIG. 4C).
  • a photosensitive resist is formed on the surface of the uniform-thickness conductor layer 7 in order to selectively remove the desired position of the uniform-thickness conductor layer 7, and a desired portion to be selectively removed by exposure and development. After the etching resist was removed, the remaining portion of the resist was used as an etching mask and treated with an etching solution for dissolving the uniform-thickness conductor layer 7.
  • the photosensitive etching resist suitable for the present invention may be a material that can obtain a desired shape and resolution, so that it is not necessary to use a special material, but it can be formed with a film thickness of 10 micrometers or less.
  • a resist is desirable. This is because when the film thickness exceeds 10 micrometers, the risk that the size of the resist opening width and the density of the opening affect the etching shape and the film thickness uniformity of the etching shape increases.
  • a positive dry film resist having a film thickness of 2.3 ⁇ m is used, and an etching solution of a sulfuric acid-hydrogen peroxide mixture system is used to remove the Cu film having a thickness of 4.9 ⁇ m.
  • the etching on the upper side proceeds faster than the etching on the lower side (the side in close contact with the substrate). Formed spontaneously.
  • the bump 2 having a uniform inclination angle 8 in the surface could be formed.
  • the remaining Cr film between the bumps 2 is removed by etching with an alkaline Cr etching solution, and finally the resist is peeled off, whereby the conductor bumps having sharp points are formed.
  • the first semiconductor element substrate 1 in which 2 was formed at a desired location could be produced.
  • FIG. 4 is omitted because it is a schematic structural diagram, but it is needless to point out that a 75 nm thick Cr film remains at the boundary between the conductor bump 2 and the semiconductor element substrate 1. .
  • an antioxidant film may be formed on the surface of the conductor bump 2 in order to suppress surface oxidation that causes a decrease in the bonding property of the conductor bump 2 having a sharp tip.
  • the conductor bump 2 is a precisely controlled fine-cone-shaped Cu, it is possible to form a film simply and at low cost, without affecting the bonding property, and An Sn plating film serving as an antioxidant film having a good surface slip was formed by a displacement plating method.
  • a film other than Sn may be used as long as the anti-slip film has good surface slipperiness and low cost.
  • Organic anti-oxidation coatings such as preflux and so-called OSP (Organic Solderability Preservative) have a good anti-oxidation effect but are insufficient in terms of surface slipping, and are therefore not preferred for application to the present invention. .
  • the bump 2 having a sharp tip shape is manufactured by a wet etching method, so that the bump 2 having a uniform shape can be manufactured at low cost, and the shape cloth of the bump 2 is caused by nonuniformity. It was possible to suppress the decrease in bonding yield. Such yield reduction suppression exhibits a special effect in terms of manufacturing yield, manufacturing cost, and quality in the multi-layer laminated structure described later.
  • FIG. 5 is a diagram showing a schematic cross-sectional structure for explaining a manufacturing method for producing the conductor bump 4 on the second semiconductor element substrate 3, and FIG. 5 (a) shows the second structure used in this embodiment.
  • 2 is a schematic view showing a cross-sectional structure of a semiconductor element substrate 3.
  • FIG. Although the detailed structure is omitted here, at least one semiconductor circuit is formed on the second semiconductor element substrate 3, and the first surface of the second semiconductor element substrate 3 is external to each semiconductor circuit.
  • An output terminal 9 is provided.
  • the second uniform-thickness conductor layer 10 is formed with a uniform thickness so as to completely cover the external output terminal 9 (FIG. 5 ( b)).
  • the second uniform-thickness conductor layer 10 is a multilayer film for convenience of the manufacturing process. It does not matter.
  • a multilayer structure composed of two kinds of materials, Cr and Cu, is employed as the uniform-thickness conductor layer 10, and continuous film formation is performed by a sputtering method in order to ensure film thickness uniformity.
  • the second uniform-thickness conductor layer 10 is a conductor film for the plating base used to produce the bumps 4 on the first surface of the second semiconductor element substrate 3, so that the plating step It is sufficient to have a film thickness that can ensure the adhesion and current density distribution required for the above.
  • a 75 nm thick Cr film was used as the adhesion film
  • a 500 nm thick Cu film was used as the conductor film.
  • a conductor bump 4 is formed at a desired position of the second uniform film thickness conductor layer 10 (FIG. 5C).
  • a photosensitive resist is formed on the surface of the uniform-thickness conductor layer 10 in order to selectively grow a conductor structure that selectively becomes bumps 4 at desired positions of the uniform-thickness conductor layer 10.
  • a predetermined exposure and development process is performed on the photosensitive resist to remove the resist at a desired portion, and then a conductor to be the bump 4 is grown by plating using the remaining portion of the resist as a plating resist mask.
  • the metallic conductor bump 4 provided on the second semiconductor element substrate 3 uses a composite structure made of at least three kinds of materials.
  • a three-layer continuous plating technique of the height matching layer 4a, the soft metal layer 4b, and the top layer 4c is applied, and about 4 micron is applied.
  • the height matching layer 4a has a metric thickness
  • the soft metal layer 4b has a thickness of about 3.8 micrometers
  • the top layer 4c has a thickness of 0.05 to 0.40 micrometers.
  • the photosensitive plating resist suitable for the present invention may be any material that can obtain a desired shape and resolution, so that it is not necessary to use a special material, but a film thickness of 10 micrometers or more is 20 micrometers. It is desirable that the resist has a resolution of a certain degree. In this embodiment, such a resist is used by forming a film with a film thickness exceeding 10 ⁇ m. When the film thickness is less than 10 micrometers, the above-described height matching layer 4a (film thickness 4 micrometers), soft metal layer 4b (film thickness 3.8 micrometers), and top layer 4c (film thickness 0.05-0. This is because it becomes difficult to apply to 40-micrometer) three-layer continuous plating.
  • a negative dry film resist having a thickness of 14.8 micrometers is used, and the height matching layer 4a having a thickness of 4 micrometers is plated with nickel sulfamate and a soft metal having a thickness of 3.8 micrometers.
  • Indium sulfate-based acidic indium plating was applied to the layer 4b, and flash silver plating was applied to the top layer 4c. After performing a predetermined three-layer continuous plating process, resist removal and pattern separation were performed, whereby the second semiconductor element substrate 3 in which the conductor bumps 4 having a three-layer structure were formed at desired locations could be produced.
  • FIG. 5 is omitted because it is a schematic structural diagram, but a 500 nm thick Cu conductor film and a 75 nm thick Cr film remain at the boundary between the conductor bump 4 and the semiconductor element substrate 3. There is no need to point it out again.
  • FIG. 6 shows a bonding of the bumped semiconductor element substrate 1 manufactured based on the manufacturing method described with reference to FIG. 4 and the bumped semiconductor element substrate 3 manufactured based on the manufacturing method described using FIG. It is a schematic sectional drawing for demonstrating the process to do.
  • the semiconductor element substrate 1 with the first bump and the semiconductor element substrate 3 with the second bump are arranged at the upper and lower opposing positions, and the bump positions are aligned with each other (FIG. 6A).
  • the bump 2 provided on the first bumped semiconductor element substrate 1 is moved by relatively moving the first bumped semiconductor element substrate 1 and the second bumped semiconductor element substrate 3. Is press-fitted into the bumps 4 provided on the second bumped semiconductor element substrate 3.
  • the first semiconductor element substrate 1 may be fixed and the second semiconductor element substrate 3 may be moved, in the present embodiment, the second bumped semiconductor element fixedly installed on the lower side
  • the conductor bumps 2 with sharp tips provided on the surface of the first semiconductor element substrate 1 are changed into the second bumps. It was intended to press fit into the conductor bump 4 having a soft metal layer provided on the surface of the attached semiconductor element substrate 3.
  • the first semiconductor element substrate 1 and the second semiconductor are disposed when the first semiconductor element substrate 1 is disposed on the upper side and the second semiconductor element substrate 3 is disposed on the lower side.
  • a predetermined amount of the underfill material 5 to be filled in the gap portion between the element substrates 3 is weighed, the predetermined amount of the underfill material 5 is placed on the second semiconductor element substrate 3, and then the first A process of moving the semiconductor element substrate 1 and press-fitting it was adopted.
  • the underfill material 5 is filled using a capillary phenomenon in which the gap between the semiconductor element substrates becomes a capillary.
  • the height of the conductive bump 2 having a sharp tip formed on the surface of the first semiconductor element substrate 1 is the conductor bump containing the soft metal layer formed on the surface of the second semiconductor element substrate 3.
  • the height of the bump 2 having a sharp tip is desirably in the range of 10 to 95% with respect to the total height of the soft metal layer-containing bump 4.
  • the present invention has realized a chip laminated structure in which at least two semiconductor chips are laminated and joined.
  • FIG. 7 is a schematic diagram for explaining another embodiment of the semiconductor device according to the present invention.
  • a third semiconductor element substrate 12 having bumps on both the front and back surfaces is stacked in multiple stages and mounted on the package substrate 11. 1 shows a schematic cross-section of the structure of a semiconductor device.
  • the first semiconductor in which the sharp bumps 2 are formed in the above-described Example 1. The element substrate 1 was diverted.
  • the third semiconductor element substrate 12 of the present embodiment is manufactured by applying the bump 2 and bump 4 manufacturing method described in Example 1 above. Although a detailed description is omitted, first, the bump 2 having a sharp tip is formed on the first surface of the semiconductor element substrate 12, and a plating resist is formed on the entire first surface. Thereafter, the bumps 4 including the soft metal layer can be formed on the second surface of the semiconductor element substrate 12.
  • the plating resist material formed on the entire surface of the first surface is different from the plating resist material for forming the bumps on the second surface. The occurrence of problems is suppressed.
  • the semiconductor element substrate 12 used in the present embodiment is formed with wiring for ensuring electrical connection between the bumps formed on the front and back surfaces (not shown).
  • a specific example of the wiring for ensuring electrical connection is a through-hole wiring that penetrates the semiconductor element substrate 12 in the plate thickness direction.
  • the front and back surfaces are electrically connected using fine wiring formed on the side wall surface of the semiconductor element substrate 12.

Landscapes

  • Wire Bonding (AREA)

Abstract

L'invention porte sur un procédé d'assemblage d'une pluralité de substrats de dispositif à semi-conducteur à température ambiante avec une charge légère lorsque les substrats sont électriquement connectés l'un à l'autre à la distance la plus courte à l'aide d'un grand nombre de bosses. Lorsqu'un premier substrat de dispositif à semi-conducteur agencé au-dessus est assemblé à un second substrat de dispositif à semi-conducteur agencé au-dessous par des bosses conductrices métalliques saillantes, les bosses saillantes, dont chaque extrémité a été taillée en pointe, sont ajustées à la presse dans des bosses contenant un métal mou. La bosse contenant un métal mou a une structure composite formée d'au moins trois types de matériaux pour une partie supérieure, une partie paroi latérale et une partie principale en métal mou.
PCT/JP2010/003580 2009-06-10 2010-05-28 Dispositif à semi-conducteur et son procédé de fabrication Ceased WO2010143369A1 (fr)

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JP2009138772A JP5486848B2 (ja) 2009-06-10 2009-06-10 半導体装置およびその製造方法
JP2009-138772 2009-06-10

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012253110A (ja) * 2011-06-01 2012-12-20 Sumitomo Bakelite Co Ltd 半導体装置および半導体装置の製造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2971081B1 (fr) 2011-02-02 2013-01-25 Commissariat Energie Atomique Procédé de fabrication de deux substrats relies par au moins une connexion mécanique et électriquement conductrice obtenue

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH025540A (ja) * 1988-06-24 1990-01-10 Nec Corp バンプ電極結合の形成方法
JP2001320012A (ja) * 2000-05-08 2001-11-16 Rohm Co Ltd 半導体装置
JP2006261264A (ja) * 2005-03-16 2006-09-28 Oki Electric Ind Co Ltd チップの積層方法及びその方法を使用した半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH025540A (ja) * 1988-06-24 1990-01-10 Nec Corp バンプ電極結合の形成方法
JP2001320012A (ja) * 2000-05-08 2001-11-16 Rohm Co Ltd 半導体装置
JP2006261264A (ja) * 2005-03-16 2006-09-28 Oki Electric Ind Co Ltd チップの積層方法及びその方法を使用した半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012253110A (ja) * 2011-06-01 2012-12-20 Sumitomo Bakelite Co Ltd 半導体装置および半導体装置の製造方法

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