ATE195595T1 - Wiedersynchronisierung eines superskalarprozessors - Google Patents
Wiedersynchronisierung eines superskalarprozessorsInfo
- Publication number
- ATE195595T1 ATE195595T1 AT95303668T AT95303668T ATE195595T1 AT E195595 T1 ATE195595 T1 AT E195595T1 AT 95303668 T AT95303668 T AT 95303668T AT 95303668 T AT95303668 T AT 95303668T AT E195595 T1 ATE195595 T1 AT E195595T1
- Authority
- AT
- Austria
- Prior art keywords
- processor
- instructions
- reorder buffer
- allocated
- condition
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
- Saccharide Compounds (AREA)
- Nitrogen Condensed Heterocyclic Rings (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/252,308 US5649225A (en) | 1994-06-01 | 1994-06-01 | Resynchronization of a superscalar processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE195595T1 true ATE195595T1 (de) | 2000-09-15 |
Family
ID=22955477
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT95303668T ATE195595T1 (de) | 1994-06-01 | 1995-05-30 | Wiedersynchronisierung eines superskalarprozessors |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US5649225A (de) |
| EP (1) | EP0686914B1 (de) |
| JP (1) | JP3751049B2 (de) |
| AT (1) | ATE195595T1 (de) |
| DE (1) | DE69518362T2 (de) |
Families Citing this family (81)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3494489B2 (ja) * | 1994-11-30 | 2004-02-09 | 株式会社ルネサステクノロジ | 命令処理装置 |
| CN1094610C (zh) | 1994-12-02 | 2002-11-20 | 英特尔公司 | 可以对复合操作数进行压缩操作和拆开操作的微处理器 |
| US5875324A (en) * | 1995-06-07 | 1999-02-23 | Advanced Micro Devices, Inc. | Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock |
| US5968169A (en) * | 1995-06-07 | 1999-10-19 | Advanced Micro Devices, Inc. | Superscalar microprocessor stack structure for judging validity of predicted subroutine return addresses |
| US5745724A (en) * | 1996-01-26 | 1998-04-28 | Advanced Micro Devices, Inc. | Scan chain for rapidly identifying first or second objects of selected types in a sequential list |
| US5881278A (en) * | 1995-10-30 | 1999-03-09 | Advanced Micro Devices, Inc. | Return address prediction system which adjusts the contents of return stack storage to enable continued prediction after a mispredicted branch |
| US5835744A (en) * | 1995-11-20 | 1998-11-10 | Advanced Micro Devices, Inc. | Microprocessor configured to swap operands in order to minimize dependency checking logic |
| US5864707A (en) * | 1995-12-11 | 1999-01-26 | Advanced Micro Devices, Inc. | Superscalar microprocessor configured to predict return addresses from a return stack storage |
| US5940859A (en) | 1995-12-19 | 1999-08-17 | Intel Corporation | Emptying packed data state during execution of packed data instructions |
| US6792523B1 (en) | 1995-12-19 | 2004-09-14 | Intel Corporation | Processor with instructions that operate on different data types stored in the same single logical register file |
| US5701508A (en) * | 1995-12-19 | 1997-12-23 | Intel Corporation | Executing different instructions that cause different data type operations to be performed on single logical register file |
| US5857096A (en) * | 1995-12-19 | 1999-01-05 | Intel Corporation | Microarchitecture for implementing an instruction to clear the tags of a stack reference register file |
| US5838942A (en) * | 1996-03-01 | 1998-11-17 | Hewlett-Packard Company | Panic trap system and method |
| GB2348720B (en) * | 1996-03-01 | 2000-11-22 | Hewlett Packard Co | Panic trap system and method |
| US5850567A (en) * | 1996-03-15 | 1998-12-15 | Adaptec, Inc. | Method for specifying concurrent execution of a string of I/O command blocks in a chain structure |
| US5758187A (en) * | 1996-03-15 | 1998-05-26 | Adaptec, Inc. | Method for enhancing performance of a RAID 1 read operation using a pair of I/O command blocks in a chain structure |
| US5923896A (en) * | 1996-03-15 | 1999-07-13 | Adaptec, Inc. | Method for sequencing execution of I/O command blocks in a chain structure by setting hold-off flags and configuring a counter in each I/O command block |
| US5892969A (en) * | 1996-03-15 | 1999-04-06 | Adaptec, Inc. | Method for concurrently executing a configured string of concurrent I/O command blocks within a chain to perform a raid 5 I/O operation |
| US5812877A (en) * | 1996-03-15 | 1998-09-22 | Adaptec, Inc. | I/O command block chain structure in a memory |
| US5768621A (en) * | 1996-03-15 | 1998-06-16 | Adaptec, Inc. | Chain manager for use in executing a chain of I/O command blocks |
| US5790822A (en) * | 1996-03-21 | 1998-08-04 | Intel Corporation | Method and apparatus for providing a re-ordered instruction cache in a pipelined microprocessor |
| US5745780A (en) * | 1996-03-27 | 1998-04-28 | International Business Machines Corporation | Method and apparatus for source lookup within a central processing unit |
| US5841999A (en) * | 1996-04-17 | 1998-11-24 | International Business Machines Corporation | Information handling system having a register remap structure using a content addressable table |
| US5944816A (en) * | 1996-05-17 | 1999-08-31 | Advanced Micro Devices, Inc. | Microprocessor configured to execute multiple threads including interrupt service routines |
| US5826070A (en) * | 1996-08-30 | 1998-10-20 | International Business Machines Corporation | Apparatus and method for maintaining status flags and condition codes using a renaming technique in an out of order floating point execution unit |
| US5870579A (en) * | 1996-11-18 | 1999-02-09 | Advanced Micro Devices, Inc. | Reorder buffer including a circuit for selecting a designated mask corresponding to an instruction that results in an exception |
| US5920710A (en) * | 1996-11-18 | 1999-07-06 | Advanced Micro Devices, Inc. | Apparatus and method for modifying status bits in a reorder buffer with a large speculative state |
| US6175906B1 (en) | 1996-12-06 | 2001-01-16 | Advanced Micro Devices, Inc. | Mechanism for fast revalidation of virtual tags |
| US5768555A (en) * | 1997-02-20 | 1998-06-16 | Advanced Micro Devices, Inc. | Reorder buffer employing last in buffer and last in line bits |
| US5887185A (en) * | 1997-03-19 | 1999-03-23 | Advanced Micro Devices, Inc. | Interface for coupling a floating point unit to a reorder buffer |
| US6085305A (en) * | 1997-06-25 | 2000-07-04 | Sun Microsystems, Inc. | Apparatus for precise architectural update in an out-of-order processor |
| US5963977A (en) * | 1997-10-09 | 1999-10-05 | Quantum Corporation | Buffer management and system coordination method |
| US6157986A (en) * | 1997-12-16 | 2000-12-05 | Advanced Micro Devices, Inc. | Fast linear tag validation unit for use in microprocessor |
| US6195722B1 (en) * | 1998-01-26 | 2001-02-27 | Intel Corporation | Method and apparatus for deferring transactions on a host bus having a third party agent |
| US6014743A (en) * | 1998-02-05 | 2000-01-11 | Intergrated Device Technology, Inc. | Apparatus and method for recording a floating point error pointer in zero cycles |
| US6260124B1 (en) * | 1998-08-13 | 2001-07-10 | International Business Machines Corporation | System and method for dynamically resynchronizing backup data |
| US6154832A (en) * | 1998-12-04 | 2000-11-28 | Advanced Micro Devices, Inc. | Processor employing multiple register sets to eliminate interrupts |
| SE521071C2 (sv) * | 1999-01-11 | 2003-09-30 | Ericsson Telefon Ab L M | Resultatfältskö |
| US6393536B1 (en) | 1999-05-18 | 2002-05-21 | Advanced Micro Devices, Inc. | Load/store unit employing last-in-buffer indication for rapid load-hit-store |
| US6298436B1 (en) * | 1999-06-08 | 2001-10-02 | International Business Machines Corporation | Method and system for performing atomic memory accesses in a processor system |
| JP2000353092A (ja) * | 1999-06-09 | 2000-12-19 | Nec Corp | 情報処理装置及びそのレジスタファイル切替方法 |
| US6385719B1 (en) * | 1999-06-30 | 2002-05-07 | International Business Machines Corporation | Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor |
| US6668315B1 (en) * | 1999-11-26 | 2003-12-23 | Hewlett-Packard Development Company, L.P. | Methods and apparatus for exchanging the contents of registers |
| US6694425B1 (en) * | 2000-05-04 | 2004-02-17 | International Business Machines Corporation | Selective flush of shared and other pipeline stages in a multithread processor |
| US7360028B1 (en) * | 2000-05-05 | 2008-04-15 | Sun Microsystems, Inc. | Explicit store-to-instruction-space instruction for self-modifying code and ensuring memory coherence between instruction cache and shared memory using a no-snoop protocol |
| US6738795B1 (en) * | 2000-05-30 | 2004-05-18 | Hewlett-Packard Development Company, L.P. | Self-timed transmission system and method for processing multiple data sets |
| SE0003446L (sv) | 2000-09-27 | 2002-03-28 | Ericsson Telefon Ab L M | En pipelinemikroprocessor och ett förfarnade relaterande därtill |
| US6564298B2 (en) * | 2000-12-22 | 2003-05-13 | Intel Corporation | Front end system having multiple decoding modes |
| US6654861B2 (en) * | 2001-07-18 | 2003-11-25 | Smart Matic Corp. | Method to manage multiple communication queues in an 8-bit microcontroller |
| US7634640B2 (en) * | 2002-08-30 | 2009-12-15 | Infineon Technologies Ag | Data processing apparatus having program counter sensor |
| US7191320B2 (en) * | 2003-02-11 | 2007-03-13 | Via Technologies, Inc. | Apparatus and method for performing a detached load operation in a pipeline microprocessor |
| US7281120B2 (en) * | 2004-03-26 | 2007-10-09 | International Business Machines Corporation | Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor |
| US7370181B2 (en) * | 2004-06-22 | 2008-05-06 | Intel Corporation | Single stepping a virtual machine guest using a reorder buffer |
| US20060168291A1 (en) * | 2005-01-05 | 2006-07-27 | Van Zoest Alexander | Interactive multichannel data distribution system |
| US7788420B2 (en) * | 2005-09-22 | 2010-08-31 | Lsi Corporation | Address buffer mode switching for varying request sizes |
| US7490224B2 (en) * | 2005-10-07 | 2009-02-10 | International Business Machines Corporation | Time-of-life counter design for handling instruction flushes from a queue |
| US20070130448A1 (en) * | 2005-12-01 | 2007-06-07 | Intel Corporation | Stack tracker |
| US8335810B2 (en) | 2006-01-31 | 2012-12-18 | Qualcomm Incorporated | Register-based shifts for a unidirectional rotator |
| US20070204142A1 (en) * | 2006-02-27 | 2007-08-30 | Dieffenderfer James N | Method and apparatus for repairing a link stack |
| US7603527B2 (en) * | 2006-09-29 | 2009-10-13 | Intel Corporation | Resolving false dependencies of speculative load instructions |
| US20080244244A1 (en) * | 2007-03-30 | 2008-10-02 | Advanced Micro Devices, Inc. | Parallel instruction processing and operand integrity verification |
| US8495699B2 (en) | 2008-12-23 | 2013-07-23 | At&T Intellectual Property I, L.P. | Distributed content analysis network |
| US20100223660A1 (en) * | 2009-02-27 | 2010-09-02 | At&T Intellectual Property I, L.P. | Providing multimedia content with time limit restrictions |
| US20100223673A1 (en) * | 2009-02-27 | 2010-09-02 | At&T Intellectual Property I, L.P. | Providing multimedia content with access restrictions |
| US8966228B2 (en) * | 2009-03-20 | 2015-02-24 | Arm Limited | Instruction fetching following changes in program flow |
| US8904421B2 (en) * | 2009-06-30 | 2014-12-02 | At&T Intellectual Property I, L.P. | Shared multimedia experience including user input |
| US8549267B2 (en) * | 2009-12-22 | 2013-10-01 | Intel Corporation | Methods and apparatus to manage partial-commit checkpoints with fixup support |
| US9880848B2 (en) * | 2010-06-11 | 2018-01-30 | Advanced Micro Devices, Inc. | Processor support for hardware transactional memory |
| US9977596B2 (en) | 2012-12-27 | 2018-05-22 | Dropbox, Inc. | Predictive models of file access patterns by application and file type |
| US9336003B2 (en) * | 2013-01-25 | 2016-05-10 | Apple Inc. | Multi-level dispatch for a superscalar processor |
| GB2514618B (en) * | 2013-05-31 | 2020-11-11 | Advanced Risc Mach Ltd | Data processing systems |
| US10390010B1 (en) * | 2013-06-12 | 2019-08-20 | Ovics | Video coding reorder buffer systems and methods |
| EP3060979B1 (de) * | 2013-10-25 | 2020-08-05 | Advanced Micro Devices, Inc. | Prozessor und verfahren zur sofortigen markierungshandhabung |
| CN108476155B (zh) * | 2015-12-25 | 2021-05-14 | 新唐科技日本株式会社 | 不正当消息检测装置、方法、记录介质、以及电子控制装置 |
| US10095637B2 (en) * | 2016-09-15 | 2018-10-09 | Advanced Micro Devices, Inc. | Speculative retirement of post-lock instructions |
| US10353707B2 (en) | 2017-07-12 | 2019-07-16 | International Business Machines Corporation | Efficient pointer load and format |
| US11068612B2 (en) | 2018-08-01 | 2021-07-20 | International Business Machines Corporation | Microarchitectural techniques to mitigate cache-based data security vulnerabilities |
| JP7131313B2 (ja) * | 2018-11-09 | 2022-09-06 | 富士通株式会社 | 演算処理装置および演算処理装置の制御方法 |
| US11561982B2 (en) * | 2020-02-19 | 2023-01-24 | Sap Se | Intelligent and automatic exception handling |
| CN117908968A (zh) * | 2022-10-11 | 2024-04-19 | 深圳市中兴微电子技术有限公司 | 基于压缩型发射队列的指令发送方法、装置、设备及介质 |
| CN119829420B (zh) * | 2024-11-27 | 2025-10-31 | 北京计算机技术及应用研究所 | 一种浮点型数据接口测试方法和装置 |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4928223A (en) * | 1982-10-06 | 1990-05-22 | Fairchild Semiconductor Corporation | Floating point microprocessor with directable two level microinstructions |
| US4807115A (en) * | 1983-10-07 | 1989-02-21 | Cornell Research Foundation, Inc. | Instruction issuing mechanism for processors with multiple functional units |
| JPH0658631B2 (ja) * | 1983-12-19 | 1994-08-03 | 株式会社日立製作所 | デ−タ処理装置 |
| EP0239081B1 (de) * | 1986-03-26 | 1995-09-06 | Hitachi, Ltd. | Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen |
| US4926322A (en) * | 1987-08-03 | 1990-05-15 | Compag Computer Corporation | Software emulation of bank-switched memory using a virtual DOS monitor and paged memory management |
| US5056006A (en) * | 1988-09-12 | 1991-10-08 | General Electric Company | Parallel processor with single program storage and sequencer and simultaneous instruction processing |
| US5067069A (en) * | 1989-02-03 | 1991-11-19 | Digital Equipment Corporation | Control of multiple functional units with parallel operation in a microcoded execution unit |
| US5155816A (en) * | 1989-02-10 | 1992-10-13 | Intel Corporation | Pipelined apparatus and method for controlled loading of floating point data in a microprocessor |
| US5155820A (en) * | 1989-02-21 | 1992-10-13 | Gibson Glenn A | Instruction format with designations for operand lengths of byte, half word, word, or double word encoded in address bits |
| US5226126A (en) * | 1989-02-24 | 1993-07-06 | Nexgen Microsystems | Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags |
| US5075844A (en) * | 1989-05-24 | 1991-12-24 | Tandem Computers Incorporated | Paired instruction processor precise exception handling mechanism |
| US5129067A (en) * | 1989-06-06 | 1992-07-07 | Advanced Micro Devices, Inc. | Multiple instruction decoder for minimizing register port requirements |
| US5136697A (en) * | 1989-06-06 | 1992-08-04 | Advanced Micro Devices, Inc. | System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache |
| US5251306A (en) * | 1990-01-16 | 1993-10-05 | Advanced Micro Devices, Inc. | Apparatus for controlling execution of a program in a computing device |
| US5226130A (en) * | 1990-02-26 | 1993-07-06 | Nexgen Microsystems | Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency |
| US5237700A (en) * | 1990-03-21 | 1993-08-17 | Advanced Micro Devices, Inc. | Exception handling processor for handling first and second level exceptions with reduced exception latency |
| JPH0820949B2 (ja) * | 1991-11-26 | 1996-03-04 | 松下電器産業株式会社 | 情報処理装置 |
| US5442756A (en) * | 1992-07-31 | 1995-08-15 | Intel Corporation | Branch prediction and resolution apparatus for a superscalar computer processor |
| US5434985A (en) * | 1992-08-11 | 1995-07-18 | International Business Machines Corporation | Simultaneous prediction of multiple branches for superscalar processing |
| US5367703A (en) * | 1993-01-08 | 1994-11-22 | International Business Machines Corporation | Method and system for enhanced branch history prediction accuracy in a superscalar processor system |
| IE80854B1 (en) * | 1993-08-26 | 1999-04-07 | Intel Corp | Processor ordering consistency for a processor performing out-of-order instruction execution |
| US5434987A (en) * | 1993-09-21 | 1995-07-18 | Intel Corporation | Method and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered store |
| US5574928A (en) * | 1993-10-29 | 1996-11-12 | Advanced Micro Devices, Inc. | Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments |
| DE69429061T2 (de) * | 1993-10-29 | 2002-07-18 | Advanced Micro Devices, Inc. | Superskalarmikroprozessoren |
-
1994
- 1994-06-01 US US08/252,308 patent/US5649225A/en not_active Expired - Fee Related
-
1995
- 1995-05-30 DE DE69518362T patent/DE69518362T2/de not_active Expired - Fee Related
- 1995-05-30 AT AT95303668T patent/ATE195595T1/de active
- 1995-05-30 EP EP95303668A patent/EP0686914B1/de not_active Expired - Lifetime
- 1995-05-31 JP JP13401095A patent/JP3751049B2/ja not_active Expired - Fee Related
-
1997
- 1997-02-10 US US08/797,434 patent/US5764938A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE69518362D1 (de) | 2000-09-21 |
| US5764938A (en) | 1998-06-09 |
| JPH07325716A (ja) | 1995-12-12 |
| DE69518362T2 (de) | 2001-04-12 |
| EP0686914A3 (de) | 1996-12-27 |
| EP0686914B1 (de) | 2000-08-16 |
| JP3751049B2 (ja) | 2006-03-01 |
| US5649225A (en) | 1997-07-15 |
| EP0686914A2 (de) | 1995-12-13 |
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