ATE225959T1 - Verfahren und vorrichtung zur befehlsausgabe - Google Patents

Verfahren und vorrichtung zur befehlsausgabe

Info

Publication number
ATE225959T1
ATE225959T1 AT96103208T AT96103208T ATE225959T1 AT E225959 T1 ATE225959 T1 AT E225959T1 AT 96103208 T AT96103208 T AT 96103208T AT 96103208 T AT96103208 T AT 96103208T AT E225959 T1 ATE225959 T1 AT E225959T1
Authority
AT
Austria
Prior art keywords
instructions
instruction
execution
oldest
instruction queue
Prior art date
Application number
AT96103208T
Other languages
English (en)
Inventor
Michael C Shebanow
John Gmuender
Michael A Simone
John R F S Szeto
Takumi Maruyama
Deforest W Tovey
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of ATE225959T1 publication Critical patent/ATE225959T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Making Paper Articles (AREA)
  • Control Of Vending Devices And Auxiliary Devices For Vending Devices (AREA)
  • Separation By Low-Temperature Treatments (AREA)
  • Electrotherapy Devices (AREA)
AT96103208T 1995-03-03 1996-03-01 Verfahren und vorrichtung zur befehlsausgabe ATE225959T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US39789195A 1995-03-03 1995-03-03

Publications (1)

Publication Number Publication Date
ATE225959T1 true ATE225959T1 (de) 2002-10-15

Family

ID=23573091

Family Applications (1)

Application Number Title Priority Date Filing Date
AT96103208T ATE225959T1 (de) 1995-03-03 1996-03-01 Verfahren und vorrichtung zur befehlsausgabe

Country Status (4)

Country Link
US (1) US5745726A (de)
EP (1) EP0730224B1 (de)
AT (1) ATE225959T1 (de)
DE (1) DE69624159T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6446224B1 (en) 1995-03-03 2002-09-03 Fujitsu Limited Method and apparatus for prioritizing and handling errors in a computer system
US5835747A (en) * 1996-01-26 1998-11-10 Advanced Micro Devices, Inc. Hierarchical scan logic for out-of-order load/store execution control
US6038657A (en) * 1995-10-06 2000-03-14 Advanced Micro Devices, Inc. Scan chains for out-of-order load/store execution control
US5864341A (en) * 1996-12-09 1999-01-26 International Business Machines Corporation Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwarding
US5850533A (en) * 1997-06-25 1998-12-15 Sun Microsystems, Inc. Method for enforcing true dependencies in an out-of-order processor
US5898853A (en) * 1997-06-25 1999-04-27 Sun Microsystems, Inc. Apparatus for enforcing true dependencies in an out-of-order processor
US6334182B2 (en) * 1998-08-18 2001-12-25 Intel Corp Scheduling operations using a dependency matrix
US6247114B1 (en) * 1999-02-19 2001-06-12 Advanced Micro Devices, Inc. Rapid selection of oldest eligible entry in a queue
US6662293B1 (en) * 2000-05-23 2003-12-09 Sun Microsystems, Inc. Instruction dependency scoreboard with a hierarchical structure
US6785802B1 (en) 2000-06-01 2004-08-31 Stmicroelectronics, Inc. Method and apparatus for priority tracking in an out-of-order instruction shelf of a high performance superscalar microprocessor
GB0023698D0 (en) * 2000-09-27 2000-11-08 Univ Bristol Instruction issue in a processor
GB0023696D0 (en) * 2000-09-27 2000-11-08 Univ Bristol Computer instructions
WO2002054228A1 (en) * 2000-12-06 2002-07-11 University Of Bristol Register renaming
US6983358B2 (en) * 2001-10-23 2006-01-03 Ip-First, Llc Method and apparatus for maintaining status coherency between queue-separated functional units
JP3577052B2 (ja) * 2002-03-19 2004-10-13 株式会社東芝 命令発行装置及び命令発行方法
US7302553B2 (en) * 2003-01-23 2007-11-27 International Business Machines Corporation Apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue
US7308562B2 (en) * 2003-05-22 2007-12-11 International Business Machines Corporation System and method for improved branch performance in pipelined computer architectures
US20070198812A1 (en) * 2005-09-27 2007-08-23 Ibm Corporation Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system
US7350056B2 (en) * 2005-09-27 2008-03-25 International Business Machines Corporation Method and apparatus for issuing instructions from an issue queue in an information handling system
US7904789B1 (en) * 2006-03-31 2011-03-08 Guillermo Rozas Techniques for detecting and correcting errors in a memory device
US7380104B2 (en) * 2006-04-25 2008-05-27 International Business Machines Corporation Method and apparatus for back to back issue of dependent instructions in an out of order issue queue
US8037366B2 (en) * 2009-03-24 2011-10-11 International Business Machines Corporation Issuing instructions in-order in an out-of-order processor using false dependencies
US20140129806A1 (en) * 2012-11-08 2014-05-08 Advanced Micro Devices, Inc. Load/store picker
US11086628B2 (en) * 2016-08-15 2021-08-10 Advanced Micro Devices, Inc. System and method for load and store queue allocations at address generation time
US11023242B2 (en) * 2017-01-27 2021-06-01 Ati Technologies Ulc Method and apparatus for asynchronous scheduling

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4992938A (en) * 1987-07-01 1991-02-12 International Business Machines Corporation Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers
US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
US5150470A (en) * 1989-12-20 1992-09-22 International Business Machines Corporation Data processing system with instruction queue having tags indicating outstanding data status
JPH04275628A (ja) * 1991-03-01 1992-10-01 Mitsubishi Electric Corp 演算処理装置
US5522052A (en) * 1991-07-04 1996-05-28 Matsushita Electric Industrial Co. Ltd. Pipeline processor for processing instructions having a data dependence relationship
JPH0820949B2 (ja) * 1991-11-26 1996-03-04 松下電器産業株式会社 情報処理装置

Also Published As

Publication number Publication date
DE69624159T2 (de) 2003-06-18
US5745726A (en) 1998-04-28
EP0730224B1 (de) 2002-10-09
EP0730224A3 (de) 1997-05-28
EP0730224A2 (de) 1996-09-04
DE69624159D1 (de) 2002-11-14

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Legal Events

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