ATE266884T1 - Hochgeschwindigkeits-prozessorsystem, verfahren zu dessen verwendung und aufzeichnungsmedium - Google Patents

Hochgeschwindigkeits-prozessorsystem, verfahren zu dessen verwendung und aufzeichnungsmedium

Info

Publication number
ATE266884T1
ATE266884T1 AT00900858T AT00900858T ATE266884T1 AT E266884 T1 ATE266884 T1 AT E266884T1 AT 00900858 T AT00900858 T AT 00900858T AT 00900858 T AT00900858 T AT 00900858T AT E266884 T1 ATE266884 T1 AT E266884T1
Authority
AT
Austria
Prior art keywords
processor system
recording medium
speed processor
high speed
cpu
Prior art date
Application number
AT00900858T
Other languages
English (en)
Inventor
Akio Ohba
Original Assignee
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc filed Critical Sony Computer Entertainment Inc
Application granted granted Critical
Publication of ATE266884T1 publication Critical patent/ATE266884T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30047—Prefetch instructions; cache control instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7821—Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Multi Processors (AREA)
AT00900858T 1999-01-21 2000-01-21 Hochgeschwindigkeits-prozessorsystem, verfahren zu dessen verwendung und aufzeichnungsmedium ATE266884T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1348699 1999-01-21
PCT/JP2000/000278 WO2000043902A1 (en) 1999-01-21 2000-01-21 High-speed processor system, method of using the same, and recording medium

Publications (1)

Publication Number Publication Date
ATE266884T1 true ATE266884T1 (de) 2004-05-15

Family

ID=11834461

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00900858T ATE266884T1 (de) 1999-01-21 2000-01-21 Hochgeschwindigkeits-prozessorsystem, verfahren zu dessen verwendung und aufzeichnungsmedium

Country Status (15)

Country Link
US (3) US6578110B1 (de)
EP (2) EP1161729B1 (de)
JP (1) JP3698358B2 (de)
KR (1) KR100678372B1 (de)
CN (1) CN100483389C (de)
AT (1) ATE266884T1 (de)
AU (1) AU3075600A (de)
BR (1) BR0008905A (de)
CA (1) CA2364338A1 (de)
DE (1) DE60010674T2 (de)
ES (1) ES2220386T3 (de)
HK (1) HK1039809A1 (de)
RU (1) RU2001122104A (de)
TW (1) TW472197B (de)
WO (1) WO2000043902A1 (de)

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US8301788B2 (en) * 2004-09-10 2012-10-30 Cavium, Inc. Deterministic finite automata (DFA) instruction
US8392590B2 (en) * 2004-09-10 2013-03-05 Cavium, Inc. Deterministic finite automata (DFA) processing
US20070005902A1 (en) * 2004-12-07 2007-01-04 Ocz Technology Group, Inc. Integrated sram cache for a memory module and method therefor
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US8819217B2 (en) * 2007-11-01 2014-08-26 Cavium, Inc. Intelligent graph walking
US7949683B2 (en) * 2007-11-27 2011-05-24 Cavium Networks, Inc. Method and apparatus for traversing a compressed deterministic finite automata (DFA) graph
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JP6228523B2 (ja) * 2014-09-19 2017-11-08 東芝メモリ株式会社 メモリ制御回路および半導体記憶装置
CN105718380B (zh) * 2015-07-29 2019-06-04 上海磁宇信息科技有限公司 细胞阵列计算系统
CN105718991B (zh) * 2015-07-29 2019-02-19 上海磁宇信息科技有限公司 细胞阵列计算系统
CN105718995B (zh) * 2015-07-29 2019-02-01 上海磁宇信息科技有限公司 细胞阵列计算系统及其调试方法
CN105718996B (zh) * 2015-07-29 2019-02-19 上海磁宇信息科技有限公司 细胞阵列计算系统以及其中的通信方法
CN105718992B (zh) * 2015-07-29 2019-02-19 上海磁宇信息科技有限公司 细胞阵列计算系统
CN105718994B (zh) * 2015-07-29 2019-02-19 上海磁宇信息科技有限公司 细胞阵列计算系统
CN105718993B (zh) * 2015-07-29 2019-02-19 上海磁宇信息科技有限公司 细胞阵列计算系统以及其中的通信方法
CN105740946B (zh) * 2015-07-29 2019-02-12 上海磁宇信息科技有限公司 一种应用细胞阵列计算系统实现神经网络计算的方法
CN105608490B (zh) * 2015-07-29 2018-10-26 上海磁宇信息科技有限公司 细胞阵列计算系统以及其中的通信方法
CN105718990B (zh) * 2015-07-29 2019-01-29 上海磁宇信息科技有限公司 细胞阵列计算系统以及其中细胞之间的通信方法
CN105718379B (zh) * 2015-07-29 2018-09-14 上海磁宇信息科技有限公司 细胞阵列计算系统以及其中细胞间群发通信方法
CN105718392B (zh) * 2016-01-15 2019-01-29 上海磁宇信息科技有限公司 细胞阵列文件存储系统及其文件存储设备与文件存储方法
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CN107291209B (zh) * 2016-04-01 2021-02-09 上海磁宇信息科技有限公司 细胞阵列计算系统
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JP6493318B2 (ja) * 2016-06-24 2019-04-03 株式会社デンソー データ処理システム
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KR102631380B1 (ko) * 2018-05-17 2024-02-01 에스케이하이닉스 주식회사 데이터 연산을 수행할 수 있는 다양한 메모리 장치를 포함하는 반도체 시스템
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Also Published As

Publication number Publication date
US20030217228A1 (en) 2003-11-20
JP3698358B2 (ja) 2005-09-21
US6745290B2 (en) 2004-06-01
CN100483389C (zh) 2009-04-29
TW472197B (en) 2002-01-11
CA2364338A1 (en) 2000-07-27
EP1445701A2 (de) 2004-08-11
US7028141B2 (en) 2006-04-11
HK1039809A1 (zh) 2002-05-10
RU2001122104A (ru) 2003-06-27
CN1341242A (zh) 2002-03-20
WO2000043902A1 (en) 2000-07-27
EP1161729A1 (de) 2001-12-12
JP2002535777A (ja) 2002-10-22
KR20010101628A (ko) 2001-11-14
AU3075600A (en) 2000-08-07
US6578110B1 (en) 2003-06-10
KR100678372B1 (ko) 2007-02-05
BR0008905A (pt) 2001-11-06
ES2220386T3 (es) 2004-12-16
EP1161729B1 (de) 2004-05-12
US20040215881A1 (en) 2004-10-28
DE60010674T2 (de) 2005-06-16
EP1445701A3 (de) 2009-03-25
DE60010674D1 (de) 2004-06-17

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