ATE322718T1 - Vorrichtung und verfahren zum pipeline- mehrfachspeicherzugriff - Google Patents

Vorrichtung und verfahren zum pipeline- mehrfachspeicherzugriff

Info

Publication number
ATE322718T1
ATE322718T1 AT01989874T AT01989874T ATE322718T1 AT E322718 T1 ATE322718 T1 AT E322718T1 AT 01989874 T AT01989874 T AT 01989874T AT 01989874 T AT01989874 T AT 01989874T AT E322718 T1 ATE322718 T1 AT E322718T1
Authority
AT
Austria
Prior art keywords
memory
request
clock
requests
memory block
Prior art date
Application number
AT01989874T
Other languages
English (en)
Inventor
Lawrence J Madar Iii
John R Nickolls
Ethan Mirsky
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of ATE322718T1 publication Critical patent/ATE322718T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Advance Control (AREA)
AT01989874T 2000-11-03 2001-11-02 Vorrichtung und verfahren zum pipeline- mehrfachspeicherzugriff ATE322718T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US24583100P 2000-11-03 2000-11-03

Publications (1)

Publication Number Publication Date
ATE322718T1 true ATE322718T1 (de) 2006-04-15

Family

ID=22928252

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01989874T ATE322718T1 (de) 2000-11-03 2001-11-02 Vorrichtung und verfahren zum pipeline- mehrfachspeicherzugriff

Country Status (5)

Country Link
US (1) US6976141B2 (de)
EP (1) EP1362288B1 (de)
AT (1) ATE322718T1 (de)
DE (1) DE60118617T2 (de)
WO (1) WO2002037284A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002037284A2 (en) * 2000-11-03 2002-05-10 Broadcom Corporation Pipelined multi-access memory apparatus and method
US8560795B2 (en) 2005-06-30 2013-10-15 Imec Memory arrangement for multi-processor systems including a memory queue
EP2317446A1 (de) * 2005-06-30 2011-05-04 Imec Speichervorrichtung für ein Mehrfachrechnersystem

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128342A (ja) 1985-11-29 1987-06-10 Fujitsu Ltd メモリアクセス制御方式
US5440713A (en) * 1992-05-29 1995-08-08 Industrial Technology Research Institute M-way N-port paged-interleaved memory system
JP3010947B2 (ja) * 1992-11-26 2000-02-21 日本電気株式会社 メモリアクセス制御装置
US5596740A (en) * 1995-01-26 1997-01-21 Cyrix Corporation Interleaved memory conflict resolution with accesses of variable bank widths and partial return of non-conflicting banks
US6052756A (en) * 1998-01-23 2000-04-18 Oki Electric Industry Co., Ltd. Memory page management
WO2002037284A2 (en) * 2000-11-03 2002-05-10 Broadcom Corporation Pipelined multi-access memory apparatus and method
US6691216B2 (en) * 2000-11-08 2004-02-10 Texas Instruments Incorporated Shared program memory for use in multicore DSP devices

Also Published As

Publication number Publication date
DE60118617T2 (de) 2007-07-05
EP1362288B1 (de) 2006-04-05
EP1362288A2 (de) 2003-11-19
US6976141B2 (en) 2005-12-13
WO2002037284A3 (en) 2003-09-04
US20020056032A1 (en) 2002-05-09
DE60118617D1 (de) 2006-05-18
WO2002037284A9 (en) 2003-02-06
WO2002037284A2 (en) 2002-05-10

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties