ATE339024T1 - Verfahren und anordnung zum einhalten eines abstandes zwischen kontakten - Google Patents

Verfahren und anordnung zum einhalten eines abstandes zwischen kontakten

Info

Publication number
ATE339024T1
ATE339024T1 AT03252892T AT03252892T ATE339024T1 AT E339024 T1 ATE339024 T1 AT E339024T1 AT 03252892 T AT03252892 T AT 03252892T AT 03252892 T AT03252892 T AT 03252892T AT E339024 T1 ATE339024 T1 AT E339024T1
Authority
AT
Austria
Prior art keywords
contact
distance
contacts
maintaining
arrangement
Prior art date
Application number
AT03252892T
Other languages
English (en)
Inventor
Robert F Wallace
Original Assignee
Sandisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandisk Corp filed Critical Sandisk Corp
Application granted granted Critical
Publication of ATE339024T1 publication Critical patent/ATE339024T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/70—Coupling devices
    • H01R12/7076—Coupling devices for connection between PCB and component, e.g. display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/234—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Container Filling Or Packaging Operations (AREA)
  • Connecting Device With Holders (AREA)
  • Lead Frames For Integrated Circuits (AREA)
AT03252892T 2002-05-08 2003-05-08 Verfahren und anordnung zum einhalten eines abstandes zwischen kontakten ATE339024T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/142,213 US7138583B2 (en) 2002-05-08 2002-05-08 Method and apparatus for maintaining a separation between contacts

Publications (1)

Publication Number Publication Date
ATE339024T1 true ATE339024T1 (de) 2006-09-15

Family

ID=29249831

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03252892T ATE339024T1 (de) 2002-05-08 2003-05-08 Verfahren und anordnung zum einhalten eines abstandes zwischen kontakten

Country Status (7)

Country Link
US (1) US7138583B2 (de)
EP (1) EP1361628B1 (de)
CN (1) CN100490609C (de)
AT (1) ATE339024T1 (de)
DE (1) DE60308089T2 (de)
ES (1) ES2272899T3 (de)
TW (1) TWI294146B (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7538440B2 (en) * 2003-04-30 2009-05-26 Intel Corporation Method for improved high current component interconnections
JP4479209B2 (ja) * 2003-10-10 2010-06-09 パナソニック株式会社 電子回路装置およびその製造方法並びに電子回路装置の製造装置
WO2006123554A1 (ja) * 2005-05-17 2006-11-23 Matsushita Electric Industrial Co., Ltd. フリップチップ実装体およびフリップチップ実装方法
US7615861B2 (en) 2006-03-13 2009-11-10 Sandisk Corporation Methods of promoting adhesion between transfer molded IC packages and injection molded plastics for creating over-molded memory cards
JP2009049258A (ja) * 2007-08-22 2009-03-05 Nippon Dempa Kogyo Co Ltd 電子部品の実装方法
CN101615519A (zh) * 2008-06-23 2009-12-30 深圳富泰宏精密工业有限公司 摇摆按钮
KR20120032293A (ko) * 2010-09-28 2012-04-05 삼성전자주식회사 반도체 패키지
JP2012160310A (ja) * 2011-01-31 2012-08-23 Fujitsu Component Ltd 表面実装部品及び製造方法
US20120298406A1 (en) * 2011-05-23 2012-11-29 International Business Machines Corporation Reduced stress gull wing solder joints for printed wiring board connections
CN103633457B (zh) * 2012-08-23 2015-12-02 联想(北京)有限公司 一种电子设备
US9955802B2 (en) 2015-04-08 2018-05-01 Fasteners For Retail, Inc. Divider with selectively securable track assembly
DE102016219423A1 (de) 2016-10-06 2018-04-12 Robert Bosch Gmbh Anordnung
US20200006273A1 (en) * 2018-06-28 2020-01-02 Intel Corporation Microelectronic device interconnect structure
CN113345879B (zh) * 2021-05-31 2022-07-12 Tcl华星光电技术有限公司 微型led显示面板
US20230009719A1 (en) * 2021-07-09 2023-01-12 Innolux Corporation Electronic apparatus

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3373481A (en) * 1965-06-22 1968-03-19 Sperry Rand Corp Method of electrically interconnecting conductors
US5476211A (en) 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
JP2716336B2 (ja) * 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
US5767580A (en) 1993-04-30 1998-06-16 Lsi Logic Corporation Systems having shaped, self-aligning micro-bump structures
US5508561A (en) * 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
EP0657932B1 (de) * 1993-12-13 2001-09-05 Matsushita Electric Industrial Co., Ltd. Vorrichtung mit Chipgehäuse und Verfahren zu Ihrer Herstellung
US5632631A (en) * 1994-06-07 1997-05-27 Tessera, Inc. Microelectronic contacts with asperities and methods of making same
US5874780A (en) * 1995-07-27 1999-02-23 Nec Corporation Method of mounting a semiconductor device to a substrate and a mounted structure
US5889326A (en) * 1996-02-27 1999-03-30 Nec Corporation Structure for bonding semiconductor device to substrate
JP2924830B2 (ja) * 1996-11-15 1999-07-26 日本電気株式会社 半導体装置及びその製造方法
US5795818A (en) * 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method
US6002172A (en) 1997-03-12 1999-12-14 International Business Machines Corporation Substrate structure and method for improving attachment reliability of semiconductor chips and modules
JP3421548B2 (ja) * 1997-09-10 2003-06-30 富士通株式会社 半導体ベアチップ、半導体ベアチップの製造方法、及び半導体ベアチップの実装構造
US6448665B1 (en) * 1997-10-15 2002-09-10 Kabushiki Kaisha Toshiba Semiconductor package and manufacturing method thereof
JPH11354561A (ja) * 1998-06-09 1999-12-24 Advantest Corp バンプ形成方法及びバンプ
JP3420076B2 (ja) * 1998-08-31 2003-06-23 新光電気工業株式会社 フリップチップ実装基板の製造方法及びフリップチップ実装基板及びフリップチップ実装構造
JP2000082522A (ja) 1998-09-08 2000-03-21 Smk Corp 電子部品接続用コネクタ
US6348739B1 (en) * 1999-04-28 2002-02-19 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
US6414849B1 (en) * 1999-10-29 2002-07-02 Stmicroelectronics, Inc. Low stress and low profile cavity down flip chip and wire bond BGA package
US6469394B1 (en) * 2000-01-31 2002-10-22 Fujitsu Limited Conductive interconnect structures and methods for forming conductive interconnect structures
JP2001249354A (ja) 2000-03-06 2001-09-14 Hirose Electric Co Ltd 電気コネクタ
JP2002151551A (ja) * 2000-11-10 2002-05-24 Hitachi Ltd フリップチップ実装構造、その実装構造を有する半導体装置及び実装方法
US6624457B2 (en) * 2001-07-20 2003-09-23 Intel Corporation Stepped structure for a multi-rank, stacked polymer memory device and method of making same

Also Published As

Publication number Publication date
EP1361628A1 (de) 2003-11-12
DE60308089D1 (de) 2006-10-19
EP1361628B1 (de) 2006-09-06
CN100490609C (zh) 2009-05-20
TW200306628A (en) 2003-11-16
TWI294146B (en) 2008-03-01
ES2272899T3 (es) 2007-05-01
DE60308089T2 (de) 2007-04-05
US7138583B2 (en) 2006-11-21
US20050000727A1 (en) 2005-01-06
CN1457226A (zh) 2003-11-19

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Legal Events

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