ATE361498T1 - E/a konfigurationsnachrichtentransfer in einem verbindungsbasierten computersystem - Google Patents

E/a konfigurationsnachrichtentransfer in einem verbindungsbasierten computersystem

Info

Publication number
ATE361498T1
ATE361498T1 AT04255078T AT04255078T ATE361498T1 AT E361498 T1 ATE361498 T1 AT E361498T1 AT 04255078 T AT04255078 T AT 04255078T AT 04255078 T AT04255078 T AT 04255078T AT E361498 T1 ATE361498 T1 AT E361498T1
Authority
AT
Austria
Prior art keywords
connection
computer system
configuration message
message transfer
based computer
Prior art date
Application number
AT04255078T
Other languages
English (en)
Inventor
Prashant Sethi
Kenneth Creta
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE361498T1 publication Critical patent/ATE361498T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Computer And Data Communications (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
AT04255078T 2004-05-10 2004-08-24 E/a konfigurationsnachrichtentransfer in einem verbindungsbasierten computersystem ATE361498T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/843,286 US20050262391A1 (en) 2004-05-10 2004-05-10 I/O configuration messaging within a link-based computing system

Publications (1)

Publication Number Publication Date
ATE361498T1 true ATE361498T1 (de) 2007-05-15

Family

ID=34930583

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04255078T ATE361498T1 (de) 2004-05-10 2004-08-24 E/a konfigurationsnachrichtentransfer in einem verbindungsbasierten computersystem

Country Status (7)

Country Link
US (1) US20050262391A1 (de)
EP (1) EP1596307B1 (de)
KR (1) KR100643815B1 (de)
CN (1) CN100382056C (de)
AT (1) ATE361498T1 (de)
DE (1) DE602004006235T2 (de)
TW (1) TWI310903B (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7987312B2 (en) * 2004-07-30 2011-07-26 Via Technologies, Inc. Method and apparatus for dynamically determining bit configuration
US20060155843A1 (en) 2004-12-30 2006-07-13 Glass Richard J Information transportation scheme from high functionality probe to logic analyzer
US7370135B2 (en) * 2005-11-21 2008-05-06 Intel Corporation Band configuration agent for link based computing system
US20090063894A1 (en) * 2007-08-29 2009-03-05 Billau Ronald L Autonomic PCI Express Hardware Detection and Failover Mechanism

Family Cites Families (27)

* Cited by examiner, † Cited by third party
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JPH05204830A (ja) * 1992-01-29 1993-08-13 Nec Ic Microcomput Syst Ltd 入出力制御装置
US5394556A (en) * 1992-12-21 1995-02-28 Apple Computer, Inc. Method and apparatus for unique address assignment, node self-identification and topology mapping for a directed acyclic graph
JPH06236345A (ja) * 1993-02-09 1994-08-23 Mitsubishi Electric Corp 信号伝送用バス
US5608876A (en) * 1995-05-22 1997-03-04 International Business Machines Corporation Add-in board with enable-disable expansion ROM for PCI bus computers
US5793997A (en) * 1996-01-11 1998-08-11 Hewlett-Packard Company Interface architecture for connection to a peripheral component interconnect bus
US5961623A (en) * 1996-08-29 1999-10-05 Apple Computer, Inc. Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer system
US6009488A (en) * 1997-11-07 1999-12-28 Microlinc, Llc Computer having packet-based interconnect channel
US6233641B1 (en) * 1998-06-08 2001-05-15 International Business Machines Corporation Apparatus and method of PCI routing in a bridge configuration
US6501761B1 (en) 1999-02-25 2002-12-31 Fairchild Semiconductor Corporation Modular network switch with peer-to-peer address mapping communication
US6324581B1 (en) * 1999-03-03 2001-11-27 Emc Corporation File server system using file system storage, data movers, and an exchange of meta data among data movers for file locking and direct access to shared file systems
US6389432B1 (en) * 1999-04-05 2002-05-14 Auspex Systems, Inc. Intelligent virtual volume access
US6810427B1 (en) * 1999-04-23 2004-10-26 Nortel Networks Limited Router table manager
US6516375B1 (en) * 1999-11-03 2003-02-04 Intel Corporation Peripheral component interconnect (PCI) configuration emulation for hub interface
US6526462B1 (en) * 1999-11-19 2003-02-25 Hammam Elabd Programmable multi-tasking memory management system
US6985988B1 (en) * 2000-11-09 2006-01-10 International Business Machines Corporation System-on-a-Chip structure having a multiple channel bus bridge
US6874036B2 (en) * 2001-02-08 2005-03-29 International Business Machines Corporation Network management server combining PDUs to minimize bandwidth consumption at data link layer
JP4457184B2 (ja) * 2001-02-13 2010-04-28 ネットアップ，インコーポレイテッド ストレージシステムにおけるフェイルオーバー処理
US6836813B1 (en) * 2001-11-30 2004-12-28 Advanced Micro Devices, Inc. Switching I/O node for connection in a multiprocessor computer system
US6883057B2 (en) * 2002-02-15 2005-04-19 International Business Machines Corporation Method and apparatus embedding PCI-to-PCI bridge functions in PCI devices using PCI configuration header type 0
US6915365B2 (en) * 2002-03-22 2005-07-05 Intel Corporation Mechanism for PCI I/O-initiated configuration cycles
US7979573B2 (en) * 2002-05-15 2011-07-12 Broadcom Corporation Smart routing between peers in a point-to-point link based system
US20040019704A1 (en) * 2002-05-15 2004-01-29 Barton Sano Multiple processor integrated circuit having configurable packet-based interfaces
US7080283B1 (en) * 2002-10-15 2006-07-18 Tensilica, Inc. Simultaneous real-time trace and debug for multiple processing core systems on a chip
US7380018B2 (en) * 2003-05-15 2008-05-27 Broadcom Corporation Peripheral bus transaction routing using primary and node ID routing information
US7170315B2 (en) * 2003-07-31 2007-01-30 Actel Corporation Programmable system on a chip
US7103823B2 (en) * 2003-08-05 2006-09-05 Newisys, Inc. Communication between multi-processor clusters of multi-cluster computer systems
US7210000B2 (en) * 2004-04-27 2007-04-24 Intel Corporation Transmitting peer-to-peer transactions through a coherent interface

Also Published As

Publication number Publication date
CN1696915A (zh) 2005-11-16
TWI310903B (en) 2009-06-11
TW200537306A (en) 2005-11-16
DE602004006235T2 (de) 2008-01-10
EP1596307A1 (de) 2005-11-16
DE602004006235D1 (de) 2007-06-14
CN100382056C (zh) 2008-04-16
KR20050107724A (ko) 2005-11-15
US20050262391A1 (en) 2005-11-24
EP1596307B1 (de) 2007-05-02
KR100643815B1 (ko) 2006-11-10

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties