ATE366983T1 - Stromarme programmiertechnik für einen schwebkörper-speichertransistor, speicherzelle und speichermatrix - Google Patents

Stromarme programmiertechnik für einen schwebkörper-speichertransistor, speicherzelle und speichermatrix

Info

Publication number
ATE366983T1
ATE366983T1 AT04787565T AT04787565T ATE366983T1 AT E366983 T1 ATE366983 T1 AT E366983T1 AT 04787565 T AT04787565 T AT 04787565T AT 04787565 T AT04787565 T AT 04787565T AT E366983 T1 ATE366983 T1 AT E366983T1
Authority
AT
Austria
Prior art keywords
memory
memory cell
state
floating body
low
Prior art date
Application number
AT04787565T
Other languages
English (en)
Inventor
Pierre Fazan
Serguei Okhonin
Original Assignee
Innovative Silicon Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innovative Silicon Sa filed Critical Innovative Silicon Sa
Application granted granted Critical
Publication of ATE366983T1 publication Critical patent/ATE366983T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/4016—Memory devices with silicon-on-insulator cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
AT04787565T 2003-09-24 2004-09-23 Stromarme programmiertechnik für einen schwebkörper-speichertransistor, speicherzelle und speichermatrix ATE366983T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US50567903P 2003-09-24 2003-09-24
US10/941,692 US7184298B2 (en) 2003-09-24 2004-09-15 Low power programming technique for a floating body memory transistor, memory cell, and memory array

Publications (1)

Publication Number Publication Date
ATE366983T1 true ATE366983T1 (de) 2007-08-15

Family

ID=34316804

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04787565T ATE366983T1 (de) 2003-09-24 2004-09-23 Stromarme programmiertechnik für einen schwebkörper-speichertransistor, speicherzelle und speichermatrix

Country Status (5)

Country Link
US (2) US7184298B2 (de)
EP (1) EP1671331B1 (de)
AT (1) ATE366983T1 (de)
DE (1) DE602004007536T2 (de)
WO (1) WO2005029499A2 (de)

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US20060114717A1 (en) 2006-06-01
US20050063224A1 (en) 2005-03-24
US7177175B2 (en) 2007-02-13
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US7184298B2 (en) 2007-02-27
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