ATE367077T1 - Verbesserte struktur gestapelter kontaktlöcher in mehrschichtigen elektronischen bauelementeträgern - Google Patents

Verbesserte struktur gestapelter kontaktlöcher in mehrschichtigen elektronischen bauelementeträgern

Info

Publication number
ATE367077T1
ATE367077T1 AT03787806T AT03787806T ATE367077T1 AT E367077 T1 ATE367077 T1 AT E367077T1 AT 03787806 T AT03787806 T AT 03787806T AT 03787806 T AT03787806 T AT 03787806T AT E367077 T1 ATE367077 T1 AT E367077T1
Authority
AT
Austria
Prior art keywords
conductive
electronic component
contact holes
component carriers
improved structure
Prior art date
Application number
AT03787806T
Other languages
English (en)
Inventor
Michele Castriotta
Stefano Oggioni
Gianluca Rogiani
Mauro Spreafico
Giorgio Viero
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE367077T1 publication Critical patent/ATE367077T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09236—Parallel layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09381—Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0979—Redundant conductors or connections, i.e. more than one current path between two points
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/209—Vertical interconnections, e.g. vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Connecting Device With Holders (AREA)
AT03787806T 2002-05-23 2003-04-18 Verbesserte struktur gestapelter kontaktlöcher in mehrschichtigen elektronischen bauelementeträgern ATE367077T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02368053 2002-05-23

Publications (1)

Publication Number Publication Date
ATE367077T1 true ATE367077T1 (de) 2007-08-15

Family

ID=31725517

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03787806T ATE367077T1 (de) 2002-05-23 2003-04-18 Verbesserte struktur gestapelter kontaktlöcher in mehrschichtigen elektronischen bauelementeträgern

Country Status (10)

Country Link
US (1) US7319197B2 (de)
EP (1) EP1506701B1 (de)
JP (1) JP4056525B2 (de)
KR (1) KR100702554B1 (de)
CN (1) CN100370887C (de)
AT (1) ATE367077T1 (de)
AU (1) AU2003276277A1 (de)
DE (1) DE60314868T2 (de)
MX (1) MXPA04011463A (de)
WO (1) WO2004017687A1 (de)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004214657A (ja) 2003-01-07 2004-07-29 Internatl Business Mach Corp <Ibm> プリント回路板製造用水溶性保護ペースト
US7652896B2 (en) * 2004-12-29 2010-01-26 Hewlett-Packard Development Company, L.P. Component for impedance matching
US20080067665A1 (en) * 2006-09-20 2008-03-20 Azniza Binti Abd Aziz Via structure
US7649265B2 (en) * 2006-09-29 2010-01-19 Intel Corporation Micro-via structure design for high performance integrated circuits
US7531373B2 (en) 2007-09-19 2009-05-12 Micron Technology, Inc. Methods of forming a conductive interconnect in a pixel of an imager and in other integrated circuitry
US8242593B2 (en) * 2008-01-27 2012-08-14 International Business Machines Corporation Clustered stacked vias for reliable electronic substrates
CN101562951B (zh) * 2008-04-18 2011-05-11 欣兴电子股份有限公司 线路板及其制作方法
JP5397007B2 (ja) * 2009-05-14 2014-01-22 富士通株式会社 プリント配線板および電子部品パッケージ
US8735734B2 (en) * 2009-07-23 2014-05-27 Lexmark International, Inc. Z-directed delay line components for printed circuit boards
US8198547B2 (en) 2009-07-23 2012-06-12 Lexmark International, Inc. Z-directed pass-through components for printed circuit boards
KR101161971B1 (ko) * 2010-07-21 2012-07-04 삼성전기주식회사 다층 회로 기판 및 다층 회로 기판의 제조 방법
KR101696644B1 (ko) * 2010-09-15 2017-01-16 삼성전자주식회사 3차원 수직 배선을 이용한 ｒｆ 적층 모듈 및 이의 배치 방법
US8790520B2 (en) 2011-08-31 2014-07-29 Lexmark International, Inc. Die press process for manufacturing a Z-directed component for a printed circuit board
US8658245B2 (en) 2011-08-31 2014-02-25 Lexmark International, Inc. Spin coat process for manufacturing a Z-directed component for a printed circuit board
US8752280B2 (en) 2011-09-30 2014-06-17 Lexmark International, Inc. Extrusion process for manufacturing a Z-directed component for a printed circuit board
US9078374B2 (en) 2011-08-31 2015-07-07 Lexmark International, Inc. Screening process for manufacturing a Z-directed component for a printed circuit board
US9009954B2 (en) 2011-08-31 2015-04-21 Lexmark International, Inc. Process for manufacturing a Z-directed component for a printed circuit board using a sacrificial constraining material
US8943684B2 (en) * 2011-08-31 2015-02-03 Lexmark International, Inc. Continuous extrusion process for manufacturing a Z-directed component for a printed circuit board
JP5765633B2 (ja) * 2011-12-22 2015-08-19 株式会社フジクラ プリント配線板及びその製造方法
TWI449475B (zh) * 2012-01-09 2014-08-11 Novatek Microelectronics Corp 電路板
US8822840B2 (en) 2012-03-29 2014-09-02 Lexmark International, Inc. Z-directed printed circuit board components having conductive channels for controlling transmission line impedance
US8912452B2 (en) 2012-03-29 2014-12-16 Lexmark International, Inc. Z-directed printed circuit board components having different dielectric regions
US8822838B2 (en) 2012-03-29 2014-09-02 Lexmark International, Inc. Z-directed printed circuit board components having conductive channels for reducing radiated emissions
US8830692B2 (en) 2012-03-29 2014-09-09 Lexmark International, Inc. Ball grid array systems for surface mounting an integrated circuit using a Z-directed printed circuit board component
CN103974519B (zh) * 2013-01-29 2017-02-08 江苏传艺科技股份有限公司 印刷电路板
TW201431450A (zh) * 2013-01-29 2014-08-01 Hon Hai Prec Ind Co Ltd 印刷電路板
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9871017B2 (en) * 2016-01-04 2018-01-16 Infineon Technologies Ag Multi-level chip interconnect
JP6674016B2 (ja) * 2016-03-24 2020-04-01 京セラ株式会社 印刷配線板およびその製造方法
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
JP6730960B2 (ja) * 2017-05-24 2020-07-29 日本特殊陶業株式会社 配線基板
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US10916519B2 (en) 2018-06-08 2021-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method for manufacturing semiconductor package with connection structures including via groups
DE102018126131A1 (de) 2018-06-08 2019-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-Packages und Verfahren zu deren Bildung
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
WO2020010136A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
JP6869209B2 (ja) * 2018-07-20 2021-05-12 日本特殊陶業株式会社 配線基板
US10727190B2 (en) * 2018-12-27 2020-07-28 Tektronix, Inc. Compound via RF transition structure in a multilayer high-density interconnect
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11776899B2 (en) 2020-05-11 2023-10-03 Mediatek Inc. Via array design for multi-layer redistribution circuit structure
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
TWI811053B (zh) * 2022-08-04 2023-08-01 矽品精密工業股份有限公司 承載結構
US12588146B2 (en) * 2022-08-25 2026-03-24 Nvidia Corporation Clustered microvia structure for a high-density interface PCB
US12616041B2 (en) * 2022-10-14 2026-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor and method for forming the same
JP7448060B1 (ja) 2023-03-27 2024-03-12 Toto株式会社 静電チャック
WO2026005028A1 (ja) * 2024-06-28 2026-01-02 京セラ株式会社 支持部材、静電チャック、ヒータおよびプラズマ処理装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8803923D0 (en) * 1988-02-19 1988-03-23 Gen Electric Co Plc Optical storage devices
JPH0797705B2 (ja) * 1989-07-17 1995-10-18 日本電気株式会社 多層セラミツク基板
JPH03142896A (ja) 1989-10-27 1991-06-18 Fujitsu Ltd 多層回路基板
JP2767645B2 (ja) * 1990-03-07 1998-06-18 富士通株式会社 多層配線基板の製造方法
JP2503725B2 (ja) * 1990-05-18 1996-06-05 日本電気株式会社 多層配線基板
JPH06326471A (ja) 1993-05-17 1994-11-25 Sony Corp 多層配線基板
US5378927A (en) * 1993-05-24 1995-01-03 International Business Machines Corporation Thin-film wiring layout for a non-planar thin-film structure
JPH088393A (ja) * 1994-06-23 1996-01-12 Fujitsu Ltd 半導体装置
US5699613A (en) * 1995-09-25 1997-12-23 International Business Machines Corporation Fine dimension stacked vias for a multiple layer circuit board structure
JPH1174651A (ja) * 1997-03-13 1999-03-16 Ibiden Co Ltd プリント配線板及びその製造方法
JP3961092B2 (ja) * 1997-06-03 2007-08-15 株式会社東芝 複合配線基板、フレキシブル基板、半導体装置、および複合配線基板の製造方法
JP3562568B2 (ja) * 1999-07-16 2004-09-08 日本電気株式会社 多層配線基板
US6362438B1 (en) * 1999-12-15 2002-03-26 Intel Corporation Enhanced plated-through hole and via contact design
US7091424B2 (en) * 2002-10-10 2006-08-15 International Business Machines Corporation Coaxial via structure for optimizing signal transmission in multiple layer electronic device carriers

Also Published As

Publication number Publication date
WO2004017687A1 (en) 2004-02-26
DE60314868D1 (de) 2007-08-23
MXPA04011463A (es) 2005-07-01
CN100370887C (zh) 2008-02-20
US20050156319A1 (en) 2005-07-21
CN1656861A (zh) 2005-08-17
KR100702554B1 (ko) 2007-04-04
AU2003276277A1 (en) 2004-03-03
KR20050009998A (ko) 2005-01-26
JP2005527122A (ja) 2005-09-08
JP4056525B2 (ja) 2008-03-05
EP1506701B1 (de) 2007-07-11
DE60314868T2 (de) 2008-03-13
US7319197B2 (en) 2008-01-15
EP1506701A1 (de) 2005-02-16

Similar Documents

Publication Publication Date Title
ATE367077T1 (de) Verbesserte struktur gestapelter kontaktlöcher in mehrschichtigen elektronischen bauelementeträgern
CA2422677A1 (en) Technique for reducing the number of layers in a multilayer circuit board
US6573600B2 (en) Multilayer wiring substrate having differential signal wires and a general signal wire in different planes
KR101213184B1 (ko) 전자 기판의 동심 비아
WO2002019430A3 (en) Hybrid substrate with embedded capacitors and methods of manufacture
TW200501182A (en) A capacitor structure
MY125677A (en) Multilayer printed circuit board
WO2006052330A3 (en) Illumination assembly with circuitized strips
JP2004235629A (ja) 高速性能を有する印刷回路基板とその製造方法
EP1605739A4 (de) Leiterplatte mit starrer nachgiebigkeit
ATE553636T1 (de) Leiterplattentopologie für eine hochfrequenzschaltung
DK1178595T3 (da) Kredslöbsindretning med lav induktivitet
TW200701853A (en) Structure of circuit board and method for fabricating the same
TW200627653A (en) Interconnection structure through passive component
AU2002360943A1 (en) Electronic device carrier adapted for transmitting high frequency signals
TW200420203A (en) Multilayer board and its manufacturing method
US20060237228A1 (en) Printed circuit board having reduced parasitic capacitance pad
TW200610466A (en) Method for fabricating conductive bumps of a circuit board
WO2000068972A3 (en) Method of creating an electrical interconnect device bearing an array of electrical contact pads
JP2001352269A5 (de)
US7649745B2 (en) Circuit board including stubless signal paths and method of making same
JP2000012738A5 (de)
JP2005276859A (ja) 高周波用配線基板
JP2005064027A (ja) 配線基板
KR100632733B1 (ko) 인쇄회로기판

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties