ATE404923T1 - Eine anordnung, um in einem datenprozessor den zugriff zu steuern - Google Patents

Eine anordnung, um in einem datenprozessor den zugriff zu steuern

Info

Publication number
ATE404923T1
ATE404923T1 AT02721883T AT02721883T ATE404923T1 AT E404923 T1 ATE404923 T1 AT E404923T1 AT 02721883 T AT02721883 T AT 02721883T AT 02721883 T AT02721883 T AT 02721883T AT E404923 T1 ATE404923 T1 AT E404923T1
Authority
AT
Austria
Prior art keywords
port
processor
switching element
data processor
arrangement
Prior art date
Application number
AT02721883T
Other languages
English (en)
Inventor
Malcolm Stewart
Eric Giernalczyk
Richard Beriault
Original Assignee
Mtek Vision Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mtek Vision Co Ltd filed Critical Mtek Vision Co Ltd
Application granted granted Critical
Publication of ATE404923T1 publication Critical patent/ATE404923T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17375—One dimensional, e.g. linear array, ring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/382—Reconfigurable for different fixed word lengths
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)
  • Selective Calling Equipment (AREA)
  • Bus Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Information Transfer Systems (AREA)
  • Debugging And Monitoring (AREA)
  • Communication Control (AREA)
AT02721883T 2001-03-02 2002-03-04 Eine anordnung, um in einem datenprozessor den zugriff zu steuern ATE404923T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US27230101P 2001-03-02 2001-03-02

Publications (1)

Publication Number Publication Date
ATE404923T1 true ATE404923T1 (de) 2008-08-15

Family

ID=23039227

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02721883T ATE404923T1 (de) 2001-03-02 2002-03-04 Eine anordnung, um in einem datenprozessor den zugriff zu steuern

Country Status (7)

Country Link
US (2) US20040254965A1 (de)
EP (3) EP1384160A2 (de)
AT (1) ATE404923T1 (de)
AU (3) AU2002238325A1 (de)
CA (3) CA2478570A1 (de)
DE (1) DE60228223D1 (de)
WO (3) WO2002071239A2 (de)

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US20040085910A1 (en) * 2002-11-01 2004-05-06 Zarlink Semiconductor V.N. Inc. Media access control device for high efficiency ethernet backplane
US7421691B1 (en) * 2003-12-23 2008-09-02 Unisys Corporation System and method for scaling performance of a data processing system
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US7757048B2 (en) * 2005-04-29 2010-07-13 Mtekvision Co., Ltd. Data processor apparatus and memory interface
US7694114B2 (en) 2005-06-09 2010-04-06 Qualcomm Incorporated Software selectable adjustment of SIMD parallelism
US7836284B2 (en) * 2005-06-09 2010-11-16 Qualcomm Incorporated Microprocessor with automatic selection of processing parallelism mode based on width data of instructions
US8218635B2 (en) 2005-09-28 2012-07-10 Synopsys, Inc. Systolic-array based systems and methods for performing block matching in motion compensation
CN101359284B (zh) * 2006-02-06 2011-05-11 威盛电子股份有限公司 处理数个不同数据格式的乘法累加单元及其方法
US20070226455A1 (en) * 2006-03-13 2007-09-27 Cooke Laurence H Variable clocked heterogeneous serial array processor
US8656143B2 (en) 2006-03-13 2014-02-18 Laurence H. Cooke Variable clocked heterogeneous serial array processor
US8532288B2 (en) * 2006-12-01 2013-09-10 International Business Machines Corporation Selectively isolating processor elements into subsets of processor elements
WO2011118013A1 (ja) * 2010-03-25 2011-09-29 富士通株式会社 マルチコアプロセッサシステム、メモリコントローラ制御方法、およびメモリコントローラ制御プログラム
US10142124B2 (en) * 2012-05-24 2018-11-27 Infineon Technologies Ag System and method to transmit data over a bus system
US9798550B2 (en) * 2013-01-09 2017-10-24 Nxp Usa, Inc. Memory access for a vector processor
JP6308095B2 (ja) 2014-10-08 2018-04-11 富士通株式会社 演算回路及び演算回路の制御方法
US9971541B2 (en) * 2016-02-17 2018-05-15 Micron Technology, Inc. Apparatuses and methods for data movement
DE102016003362A1 (de) * 2016-03-18 2017-09-21 Giesecke+Devrient Currency Technology Gmbh Einrichtung und Verfahren zur Auswertung von Sensordaten für ein Wertdokument
US10268389B2 (en) 2017-02-22 2019-04-23 Micron Technology, Inc. Apparatuses and methods for in-memory operations
US10318168B2 (en) 2017-06-19 2019-06-11 Micron Technology, Inc. Apparatuses and methods for simultaneous in data path compute operations
US11106268B2 (en) * 2018-07-29 2021-08-31 Redpine Signals, Inc. Method and system for saving power in a real time hardware processing unit
US20230237320A1 (en) * 2020-06-05 2023-07-27 Furiosaai Inc. Neural network processing method and device therefor
US12013809B2 (en) * 2020-09-30 2024-06-18 Beijing Tsingmicro Intelligent Technology Co., Ltd. Computing array and processor having the same
US12394009B2 (en) * 2021-05-28 2025-08-19 MemComputing, Inc. Memory graphics processing unit

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Also Published As

Publication number Publication date
AU2002240742A1 (en) 2002-09-19
CA2478573A1 (en) 2002-09-12
US20040254965A1 (en) 2004-12-16
CA2478571A1 (en) 2002-09-12
CA2478570A1 (en) 2002-09-12
WO2002071246A3 (en) 2003-05-15
DE60228223D1 (de) 2008-09-25
EP1384158B1 (de) 2008-08-13
WO2002071246A2 (en) 2002-09-12
US20070118721A1 (en) 2007-05-24
WO2002071239A3 (en) 2003-04-10
EP1381957A2 (de) 2004-01-21
US7272691B2 (en) 2007-09-18
WO2002071239A2 (en) 2002-09-12
AU2002238325A1 (en) 2002-09-19
WO2002071240A2 (en) 2002-09-12
AU2002252863A1 (en) 2002-09-19
CA2478573C (en) 2010-05-25
WO2002071240A3 (en) 2003-05-30
EP1384160A2 (de) 2004-01-28
EP1384158A2 (de) 2004-01-28

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