ATE405846T1 - Fehlererkennung in komprimierten daten - Google Patents
Fehlererkennung in komprimierten datenInfo
- Publication number
- ATE405846T1 ATE405846T1 AT05101918T AT05101918T ATE405846T1 AT E405846 T1 ATE405846 T1 AT E405846T1 AT 05101918 T AT05101918 T AT 05101918T AT 05101918 T AT05101918 T AT 05101918T AT E405846 T1 ATE405846 T1 AT E405846T1
- Authority
- AT
- Austria
- Prior art keywords
- data
- dut
- data sequence
- error detection
- compressed data
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318544—Scanning methods, algorithms and patterns
- G01R31/318547—Data generators or compressors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318335—Test pattern compression or decompression
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Television Signal Processing For Recording (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP05101918A EP1701173B1 (de) | 2005-03-11 | 2005-03-11 | Fehlererkennung in komprimierten Daten |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE405846T1 true ATE405846T1 (de) | 2008-09-15 |
Family
ID=34938955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT05101918T ATE405846T1 (de) | 2005-03-11 | 2005-03-11 | Fehlererkennung in komprimierten daten |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US8473796B2 (de) |
| EP (1) | EP1701173B1 (de) |
| JP (1) | JP2006250940A (de) |
| AT (1) | ATE405846T1 (de) |
| DE (1) | DE602005009133D1 (de) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100761851B1 (ko) * | 2006-06-30 | 2007-09-28 | 삼성전자주식회사 | 실시간으로 최적화되는 반도체 소자의 전기적 검사를 위한 컴퓨터로 실행 가능한 저장매체 및 그 적용방법 |
| JP5300373B2 (ja) * | 2008-08-25 | 2013-09-25 | 株式会社東芝 | 代数的トーラスを用いたデータ圧縮処理を行う装置およびプログラム |
| FR2952735B1 (fr) * | 2009-11-18 | 2011-12-09 | St Microelectronics Rousset | Procede et dispositif de detection d'attaques par injection de fautes |
| US8582768B2 (en) | 2011-02-16 | 2013-11-12 | Marvell World Trade Ltd. | Recovery from decryption errors in a sequence of communication packets |
| FR2984553B1 (fr) | 2011-12-15 | 2015-11-06 | Proton World Int Nv | Procede et dispositif de detection de fautes |
| US9385865B2 (en) * | 2013-07-18 | 2016-07-05 | Marvell World Trade Ltd. | Correcting deciphering mis-synchronization in a mobile communication terminal |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5173906A (en) * | 1990-08-31 | 1992-12-22 | Dreibelbis Jeffrey H | Built-in self test for integrated circuits |
| DE69100204T2 (de) | 1991-11-11 | 1994-01-13 | Hewlett Packard Gmbh | Einrichtung zur Erzeugung von Testsignalen. |
| DE4305442C2 (de) | 1993-02-23 | 1999-08-05 | Hewlett Packard Gmbh | Verfahren und Vorrichtung zum Erzeugen eines Testvektors |
| EP0882991B1 (de) | 1997-05-22 | 1999-03-17 | Hewlett-Packard Company | Dekompressionsschaltkreis |
| DE69700660T2 (de) | 1997-05-30 | 2000-02-10 | Hewlett-Packard Co., Palo Alto | Mehrkanalanordnung mit einem unabhängigen Taktsignal pro Kanal |
| US5930270A (en) * | 1997-07-23 | 1999-07-27 | International Business Machines Corporation | Logic built in self-test diagnostic method |
| EP0864977B1 (de) | 1997-09-13 | 1999-07-14 | Hewlett-Packard Company | Ausgleich von Latenzzeit in einem Speicher |
| EP0859318B1 (de) | 1997-09-13 | 1999-07-14 | Hewlett-Packard Company | Optimierte Speicherorganisation in einer Mehrkanalcomputerarchitektur |
| US6067651A (en) * | 1998-02-20 | 2000-05-23 | Hewlett-Packard Company | Test pattern generator having improved test sequence compaction |
| US6578169B1 (en) * | 2000-04-08 | 2003-06-10 | Advantest Corp. | Data failure memory compaction for semiconductor test system |
| JP4863547B2 (ja) * | 2000-12-27 | 2012-01-25 | ルネサスエレクトロニクス株式会社 | Bist回路内蔵半導体集積回路装置 |
| DE10122619C1 (de) * | 2001-05-10 | 2003-02-13 | Infineon Technologies Ag | Testschaltung zum Testen einer synchronen Schaltung |
| US6948096B2 (en) * | 2001-07-31 | 2005-09-20 | Intel Corporation | Functional random instruction testing (FRIT) method for complex devices such as microprocessors |
| JP2003332443A (ja) * | 2002-05-08 | 2003-11-21 | Toshiba Corp | 半導体集積回路とその設計支援装置およびテスト方法 |
| JP4031954B2 (ja) * | 2002-06-11 | 2008-01-09 | 富士通株式会社 | 集積回路の診断装置および診断方法 |
-
2005
- 2005-03-11 AT AT05101918T patent/ATE405846T1/de not_active IP Right Cessation
- 2005-03-11 EP EP05101918A patent/EP1701173B1/de not_active Expired - Lifetime
- 2005-03-11 DE DE602005009133T patent/DE602005009133D1/de not_active Expired - Lifetime
-
2006
- 2006-01-27 US US11/342,177 patent/US8473796B2/en active Active
- 2006-03-13 JP JP2006067885A patent/JP2006250940A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| EP1701173B1 (de) | 2008-08-20 |
| JP2006250940A (ja) | 2006-09-21 |
| EP1701173A1 (de) | 2006-09-13 |
| DE602005009133D1 (de) | 2008-10-02 |
| US8473796B2 (en) | 2013-06-25 |
| US20060212770A1 (en) | 2006-09-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |