ATE405947T1 - Verfahren zur herstellung vonn substraten für epitakitisches wachstum - Google Patents

Verfahren zur herstellung vonn substraten für epitakitisches wachstum

Info

Publication number
ATE405947T1
ATE405947T1 AT03292377T AT03292377T ATE405947T1 AT E405947 T1 ATE405947 T1 AT E405947T1 AT 03292377 T AT03292377 T AT 03292377T AT 03292377 T AT03292377 T AT 03292377T AT E405947 T1 ATE405947 T1 AT E405947T1
Authority
AT
Austria
Prior art keywords
substrate
base layer
growth
epitaxial
epitakitic
Prior art date
Application number
AT03292377T
Other languages
English (en)
Inventor
Takeshi Akatsu
Cecile Aulnette
Bruno Ghyselen
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE405947T1 publication Critical patent/ATE405947T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/52—Alloys
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/915—Separating from substrate

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)
AT03292377T 2003-09-26 2003-09-26 Verfahren zur herstellung vonn substraten für epitakitisches wachstum ATE405947T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03292377A EP1519409B1 (de) 2003-09-26 2003-09-26 Verfahren zur Herstellung vonn Substraten für epitakitisches Wachstum

Publications (1)

Publication Number Publication Date
ATE405947T1 true ATE405947T1 (de) 2008-09-15

Family

ID=34178652

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03292377T ATE405947T1 (de) 2003-09-26 2003-09-26 Verfahren zur herstellung vonn substraten für epitakitisches wachstum

Country Status (5)

Country Link
US (1) US7232488B2 (de)
EP (1) EP1519409B1 (de)
JP (1) JP4733201B2 (de)
AT (1) ATE405947T1 (de)
DE (1) DE60323098D1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1605498A1 (de) * 2004-06-11 2005-12-14 S.O.I. Tec Silicon on Insulator Technologies S.A. Verfahren zur Herstellung eines Halbleiterwafers
TW200733244A (en) * 2005-10-06 2007-09-01 Nxp Bv Semiconductor device
US7691730B2 (en) * 2005-11-22 2010-04-06 Corning Incorporated Large area semiconductor on glass insulator
FR2920589B1 (fr) * 2007-09-04 2010-12-03 Soitec Silicon On Insulator "procede d'obtention d'un substrat hybride comprenant au moins une couche d'un materiau nitrure"
EP2105957A3 (de) 2008-03-26 2011-01-19 Semiconductor Energy Laboratory Co., Ltd. Verfahren zur Herstellung eines SOI-Substrats und Verfahren zur Herstellung einer Halbleitervorrichtung
JP5654206B2 (ja) 2008-03-26 2015-01-14 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法及び該ｓｏｉ基板を用いた半導体装置
GB2467935B (en) * 2009-02-19 2013-10-30 Iqe Silicon Compounds Ltd Formation of thin layers of GaAs and germanium materials
KR20120112635A (ko) * 2010-01-15 2012-10-11 스미또모 가가꾸 가부시키가이샤 반도체 기판, 전자 디바이스 및 반도체 기판의 제조 방법
WO2011146015A1 (en) 2010-05-18 2011-11-24 Agency For Science, Technology And Research Method of forming a light emitting diode structure and a light emitting diode structure
RU2546858C1 (ru) * 2013-11-29 2015-04-10 Юрий Георгиевич Шретер Способ изготовления полупроводниковых приборных структур, основанный на клонировании исходных подложек (варианты)
CN109678106B (zh) * 2018-11-13 2020-10-30 中国科学院上海微系统与信息技术研究所 一种硅基异质集成4H-SiC外延薄膜结构的制备方法
FR3108204B1 (fr) * 2020-03-10 2023-10-27 Commissariat Energie Atomique Procédé de suspension d’une couche mince sur une cavité avec effet raidisseur obtenu par pressurisation de la cavité par des espèces implantées

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5362682A (en) * 1980-04-10 1994-11-08 Massachusetts Institute Of Technology Method of producing sheets of crystalline material and devices made therefrom
US6039803A (en) * 1996-06-28 2000-03-21 Massachusetts Institute Of Technology Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon
DE19802977A1 (de) * 1998-01-27 1999-07-29 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung einer einkristallinen Schicht auf einem nicht gitterangepaßten Substrat, sowie eine oder mehrere solcher Schichten enthaltendes Bauelement
US6540827B1 (en) * 1998-02-17 2003-04-01 Trustees Of Columbia University In The City Of New York Slicing of single-crystal films using ion implantation
US6641662B2 (en) * 1998-02-17 2003-11-04 The Trustees Of Columbia University In The City Of New York Method for fabricating ultra thin single-crystal metal oxide wave retarder plates and waveguide polarization mode converter using the same
CA2327421A1 (en) * 1998-04-10 1999-10-21 Jeffrey T. Borenstein Silicon-germanium etch stop layer system
EP1309989B1 (de) * 2000-08-16 2007-01-10 Massachusetts Institute Of Technology Verfahren für die herstellung eines halbleiterartikels mittels graduellem epitaktischen wachsen
US6524935B1 (en) * 2000-09-29 2003-02-25 International Business Machines Corporation Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique
US6497763B2 (en) * 2001-01-19 2002-12-24 The United States Of America As Represented By The Secretary Of The Navy Electronic device with composite substrate
JP3761418B2 (ja) * 2001-05-10 2006-03-29 Ｈｏｙａ株式会社 化合物結晶およびその製造法
FR2827423B1 (fr) * 2001-07-16 2005-05-20 Soitec Silicon On Insulator Procede d'amelioration d'etat de surface

Also Published As

Publication number Publication date
EP1519409A1 (de) 2005-03-30
JP2009290228A (ja) 2009-12-10
EP1519409B1 (de) 2008-08-20
US7232488B2 (en) 2007-06-19
JP4733201B2 (ja) 2011-07-27
DE60323098D1 (de) 2008-10-02
US20050066886A1 (en) 2005-03-31

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