ATE491225T1 - Verfahren zur herstellung dünner schichten, die mikrokomponenten enthalten - Google Patents

Verfahren zur herstellung dünner schichten, die mikrokomponenten enthalten

Info

Publication number
ATE491225T1
ATE491225T1 AT02785528T AT02785528T ATE491225T1 AT E491225 T1 ATE491225 T1 AT E491225T1 AT 02785528 T AT02785528 T AT 02785528T AT 02785528 T AT02785528 T AT 02785528T AT E491225 T1 ATE491225 T1 AT E491225T1
Authority
AT
Austria
Prior art keywords
substrate
microcomponents
thin layers
layers containing
implantation
Prior art date
Application number
AT02785528T
Other languages
English (en)
Inventor
Bernard Aspar
Chrystelle Lagahe
Bruno Ghyselen
Original Assignee
Commissariat Energie Atomique
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique, Soitec Silicon On Insulator filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE491225T1 publication Critical patent/ATE491225T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H10P54/50—Cutting or separating of wafers, substrates or parts of devices by scoring, breaking or cleaving
    • H10P54/52—Cutting or separating of wafers, substrates or parts of devices by scoring, breaking or cleaving by cleaving
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7412—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H10P72/7414—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support the auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support

Landscapes

  • Recrystallisation Techniques (AREA)
  • Physical Or Chemical Processes And Apparatus (AREA)
  • Micromachines (AREA)
  • Inorganic Compounds Of Heavy Metals (AREA)
  • Laminated Bodies (AREA)
  • Element Separation (AREA)
AT02785528T 2001-10-11 2002-10-08 Verfahren zur herstellung dünner schichten, die mikrokomponenten enthalten ATE491225T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0113105A FR2830983B1 (fr) 2001-10-11 2001-10-11 Procede de fabrication de couches minces contenant des microcomposants
PCT/FR2002/003422 WO2003032384A1 (fr) 2001-10-11 2002-10-08 Procede de fabrication de couches minces contenant des microcomposants

Publications (1)

Publication Number Publication Date
ATE491225T1 true ATE491225T1 (de) 2010-12-15

Family

ID=8868171

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02785528T ATE491225T1 (de) 2001-10-11 2002-10-08 Verfahren zur herstellung dünner schichten, die mikrokomponenten enthalten

Country Status (10)

Country Link
US (1) US7615463B2 (de)
EP (1) EP1435111B1 (de)
JP (1) JP4425631B2 (de)
KR (1) KR20040051605A (de)
CN (1) CN100440477C (de)
AT (1) ATE491225T1 (de)
DE (1) DE60238548D1 (de)
FR (1) FR2830983B1 (de)
TW (1) TWI307125B (de)
WO (1) WO2003032384A1 (de)

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FR2748851B1 (fr) 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
FR2848336B1 (fr) 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
DE60336543D1 (de) 2003-05-27 2011-05-12 Soitec Silicon On Insulator Verfahren zur Herstellung einer heteroepitaktischen Mikrostruktur
FR2856844B1 (fr) 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
US8475693B2 (en) 2003-09-30 2013-07-02 Soitec Methods of making substrate structures having a weakened intermediate layer
FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
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FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
KR101219358B1 (ko) * 2011-07-26 2013-01-21 삼성코닝정밀소재 주식회사 기판 분리 방법 및 이를 이용한 접합기판 제조방법
TWI573198B (zh) * 2011-09-27 2017-03-01 索泰克公司 在三度空間集積製程中轉移材料層之方法及其相關結構與元件
US8673733B2 (en) * 2011-09-27 2014-03-18 Soitec Methods of transferring layers of material in 3D integration processes and related structures and devices
US8841742B2 (en) 2011-09-27 2014-09-23 Soitec Low temperature layer transfer process using donor structure with material in recesses in transfer layer, semiconductor structures fabricated using such methods
US9481566B2 (en) 2012-07-31 2016-11-01 Soitec Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices
FR3074960B1 (fr) * 2017-12-07 2019-12-06 Soitec Procede de transfert d'une couche utilisant une structure demontable
FR3091620B1 (fr) * 2019-01-07 2021-01-29 Commissariat Energie Atomique Procédé de transfert de couche avec réduction localisée d’une capacité à initier une fracture
FR3094559B1 (fr) * 2019-03-29 2024-06-21 Soitec Silicon On Insulator Procédé de transfert de paves d’un substrat donneur sur un substrat receveur
US12593632B2 (en) * 2023-08-15 2026-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of implanting semiconductor donor substrate and method of manufacturing semiconductor-on-insulator structure

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Also Published As

Publication number Publication date
EP1435111A1 (de) 2004-07-07
US20050221583A1 (en) 2005-10-06
JP4425631B2 (ja) 2010-03-03
TWI307125B (en) 2009-03-01
KR20040051605A (ko) 2004-06-18
DE60238548D1 (de) 2011-01-20
CN1586004A (zh) 2005-02-23
WO2003032384A1 (fr) 2003-04-17
US7615463B2 (en) 2009-11-10
JP2005505935A (ja) 2005-02-24
FR2830983B1 (fr) 2004-05-14
EP1435111B1 (de) 2010-12-08
CN100440477C (zh) 2008-12-03
FR2830983A1 (fr) 2003-04-18

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