ATE451717T1 - Herstellungsverfahren - Google Patents

Herstellungsverfahren

Info

Publication number
ATE451717T1
ATE451717T1 AT04744316T AT04744316T ATE451717T1 AT E451717 T1 ATE451717 T1 AT E451717T1 AT 04744316 T AT04744316 T AT 04744316T AT 04744316 T AT04744316 T AT 04744316T AT E451717 T1 ATE451717 T1 AT E451717T1
Authority
AT
Austria
Prior art keywords
liquid layer
stamp
multilevel
produce
pattern
Prior art date
Application number
AT04744316T
Other languages
English (en)
Inventor
Alexander Bietsch
Bruno Michel
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE451717T1 publication Critical patent/ATE451717T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/091—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts by printing or stamping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/0882—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures wherein the dual damascene structure is in a photoresist layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/946—Step and repeat

Landscapes

  • Engineering & Computer Science (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Diffracting Gratings Or Hologram Optical Elements (AREA)
  • Drying Of Semiconductors (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
AT04744316T 2003-09-29 2004-08-23 Herstellungsverfahren ATE451717T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03021935 2003-09-29
PCT/IB2004/002724 WO2005031855A1 (en) 2003-09-29 2004-08-23 Fabrication method

Publications (1)

Publication Number Publication Date
ATE451717T1 true ATE451717T1 (de) 2009-12-15

Family

ID=34384568

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04744316T ATE451717T1 (de) 2003-09-29 2004-08-23 Herstellungsverfahren

Country Status (9)

Country Link
US (1) US7446057B2 (de)
EP (1) EP1702359B1 (de)
JP (1) JP4726789B2 (de)
KR (1) KR100791443B1 (de)
CN (1) CN100483672C (de)
AT (1) ATE451717T1 (de)
DE (1) DE602004024585D1 (de)
TW (1) TWI313490B (de)
WO (1) WO2005031855A1 (de)

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US7323417B2 (en) 2004-09-21 2008-01-29 Molecular Imprints, Inc. Method of forming a recessed structure employing a reverse tone process
US7186656B2 (en) 2004-05-21 2007-03-06 Molecular Imprints, Inc. Method of forming a recessed structure employing a reverse tone process
US7396475B2 (en) 2003-04-25 2008-07-08 Molecular Imprints, Inc. Method of forming stepped structures employing imprint lithography
US7632087B2 (en) * 2003-12-19 2009-12-15 Wd Media, Inc. Composite stamper for imprint lithography
US7547504B2 (en) 2004-09-21 2009-06-16 Molecular Imprints, Inc. Pattern reversal employing thick residual layers
US7205244B2 (en) 2004-09-21 2007-04-17 Molecular Imprints Patterning substrates employing multi-film layers defining etch-differential interfaces
US7357876B2 (en) 2004-12-01 2008-04-15 Molecular Imprints, Inc. Eliminating printability of sub-resolution defects in imprint lithography
US7875547B2 (en) * 2005-01-12 2011-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Contact hole structures and contact structures and fabrication methods thereof
JP4290177B2 (ja) 2005-06-08 2009-07-01 キヤノン株式会社 モールド、アライメント方法、パターン形成装置、パターン転写装置、及びチップの製造方法
US7256131B2 (en) 2005-07-19 2007-08-14 Molecular Imprints, Inc. Method of controlling the critical dimension of structures formed on a substrate
CN101505974A (zh) * 2005-09-07 2009-08-12 凸版光掩膜公司 用来制作双波纹结构的光掩模及其形成方法
US20070077763A1 (en) 2005-09-30 2007-04-05 Molecular Imprints, Inc. Deposition technique to planarize a multi-layer structure
GB0523163D0 (en) * 2005-11-14 2005-12-21 Suisse Electronique Microtech Patterning of conductive layers with underlying compressible spacer layer or spacer layer stack
JP4684984B2 (ja) * 2005-12-07 2011-05-18 キヤノン株式会社 半導体装置の製造方法と物品の製造方法
US7422981B2 (en) 2005-12-07 2008-09-09 Canon Kabushiki Kaisha Method for manufacturing semiconductor device by using dual damascene process and method for manufacturing article having communicating hole
WO2007100849A2 (en) 2006-02-27 2007-09-07 Microcontinuum, Inc. Formation of pattern replicating tools
US7468330B2 (en) 2006-04-05 2008-12-23 International Business Machines Corporation Imprint process using polyhedral oligomeric silsesquioxane based imprint materials
DE102006030267B4 (de) 2006-06-30 2009-04-16 Advanced Micro Devices, Inc., Sunnyvale Nano-Einprägetechnik mit erhöhter Flexibilität in Bezug auf die Justierung und die Formung von Strukturelementen
US8093150B2 (en) 2006-09-19 2012-01-10 Infineon Technologies Ag Methods of manufacturing semiconductor devices and structures thereof
TR201802198T4 (tr) 2007-01-16 2018-03-21 Koninklijke Philips Nv Bir esnek tabakanın ve bir substratın temas etmesi için yöntem ve sistem.
US9889239B2 (en) 2007-03-23 2018-02-13 Allegiance Corporation Fluid collection and disposal system and related methods
US8460256B2 (en) 2009-07-15 2013-06-11 Allegiance Corporation Collapsible fluid collection and disposal system and related methods
DK2139620T3 (en) 2007-03-23 2016-03-07 Allegiance Corp Fluidopsamlings- and disposal system and related practices
JP2009069203A (ja) * 2007-09-10 2009-04-02 Fuji Xerox Co Ltd 高分子光導波路及びその製造方法
US20170004978A1 (en) * 2007-12-31 2017-01-05 Intel Corporation Methods of forming high density metal wiring for fine line and space packaging applications and structures formed thereby
JP4977121B2 (ja) * 2008-03-25 2012-07-18 富士フイルム株式会社 インプリント用モールド構造体及びそれを用いたインプリント方法、並びに磁気記録媒体の製造方法
EP2300207A4 (de) * 2008-06-26 2012-05-09 Harvard College Mittels replikation hergestellte vielseitige betätigbare nanostrukturierte materialien
EP2172168A1 (de) * 2008-10-01 2010-04-07 3M Innovative Properties Company Dentale Vorrichtung, Verfahren zur Herstellung einer dentalen Vorrichtung und Verwendung davon
US8021974B2 (en) * 2009-01-09 2011-09-20 Internatioanl Business Machines Corporation Structure and method for back end of the line integration
BR112012006934A2 (pt) 2009-09-30 2020-08-18 3M Innovative Properties Company método e sistema para a fabricação de aparelho dentário em camadas
WO2011041194A1 (en) 2009-09-30 2011-04-07 3M Innovative Properties Company Systems and methods for making layered dental appliances
BR112012006947A2 (pt) 2009-09-30 2019-09-24 3M Innovative Properties Co método e sistema para a fabricação de uma peça dental em camadas
WO2011075349A1 (en) 2009-12-18 2011-06-23 3M Innovative Properties Company Method for making layered dental restorations
CN102214601B (zh) * 2010-04-02 2014-07-30 中芯国际集成电路制造(上海)有限公司 双镶嵌结构形成方法
FR2974194B1 (fr) * 2011-04-12 2013-11-15 Commissariat Energie Atomique Procede de lithographie
CN102760686B (zh) * 2011-04-27 2014-12-03 中芯国际集成电路制造(上海)有限公司 半导体器件、形成互连结构的方法
CN102800623A (zh) * 2011-05-26 2012-11-28 中芯国际集成电路制造(上海)有限公司 形成双镶嵌结构的方法
US9589797B2 (en) 2013-05-17 2017-03-07 Microcontinuum, Inc. Tools and methods for producing nanoantenna electronic devices
TWI664066B (zh) 2014-09-30 2019-07-01 Fujifilm Corporation 多孔質體的製造方法、元件的製造方法、配線結構的製造方法
US10892167B2 (en) * 2019-03-05 2021-01-12 Canon Kabushiki Kaisha Gas permeable superstrate and methods of using the same
FR3108780B1 (fr) * 2020-03-30 2022-03-18 Commissariat Energie Atomique Procédé de réalisation d’une zone d’individualisation d’un circuit intégré
CN120748587B (zh) * 2025-09-05 2025-10-31 山西医科大学 一种纳米孔功能性控制方法及系统

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Also Published As

Publication number Publication date
CN100483672C (zh) 2009-04-29
JP4726789B2 (ja) 2011-07-20
US20070275556A1 (en) 2007-11-29
WO2005031855A1 (en) 2005-04-07
KR20060086354A (ko) 2006-07-31
TW200512832A (en) 2005-04-01
KR100791443B1 (ko) 2008-01-10
CN1860605A (zh) 2006-11-08
EP1702359A1 (de) 2006-09-20
EP1702359B1 (de) 2009-12-09
JP2007507860A (ja) 2007-03-29
DE602004024585D1 (de) 2010-01-21
TWI313490B (en) 2009-08-11
US7446057B2 (en) 2008-11-04

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Legal Events

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