ATE421766T1 - Herstellungsverfahren für gemischte substrate und dadurch hergestellte struktur - Google Patents

Herstellungsverfahren für gemischte substrate und dadurch hergestellte struktur

Info

Publication number
ATE421766T1
ATE421766T1 AT03799685T AT03799685T ATE421766T1 AT E421766 T1 ATE421766 T1 AT E421766T1 AT 03799685 T AT03799685 T AT 03799685T AT 03799685 T AT03799685 T AT 03799685T AT E421766 T1 ATE421766 T1 AT E421766T1
Authority
AT
Austria
Prior art keywords
layer
sub
substrate
pattern
mould
Prior art date
Application number
AT03799685T
Other languages
English (en)
Inventor
Franck Fournel
Hubert Moriceau
Bernard Aspar
Marc Zussy
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE421766T1 publication Critical patent/ATE421766T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding

Landscapes

  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Prostheses (AREA)
  • Laminated Bodies (AREA)
  • Combinations Of Printed Boards (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
AT03799685T 2002-12-24 2003-12-22 Herstellungsverfahren für gemischte substrate und dadurch hergestellte struktur ATE421766T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0216646A FR2850487B1 (fr) 2002-12-24 2002-12-24 Procede de realisation de substrats mixtes et structure ainsi obtenue

Publications (1)

Publication Number Publication Date
ATE421766T1 true ATE421766T1 (de) 2009-02-15

Family

ID=32669139

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03799685T ATE421766T1 (de) 2002-12-24 2003-12-22 Herstellungsverfahren für gemischte substrate und dadurch hergestellte struktur

Country Status (7)

Country Link
US (1) US7494897B2 (de)
EP (1) EP1576658B1 (de)
JP (1) JP5188672B2 (de)
AT (1) ATE421766T1 (de)
DE (1) DE60326005D1 (de)
FR (1) FR2850487B1 (de)
WO (1) WO2004059711A1 (de)

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FR2748851B1 (fr) 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
FR2848336B1 (fr) * 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
FR2856844B1 (fr) * 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
FR2861497B1 (fr) * 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
FR2875947B1 (fr) * 2004-09-30 2007-09-07 Tracit Technologies Nouvelle structure pour microelectronique et microsysteme et procede de realisation
FR2876219B1 (fr) * 2004-10-06 2006-11-24 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.
FR2876220B1 (fr) 2004-10-06 2007-09-28 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.
FR2891281B1 (fr) * 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
FR2897982B1 (fr) 2006-02-27 2008-07-11 Tracit Technologies Sa Procede de fabrication des structures de type partiellement soi, comportant des zones reliant une couche superficielle et un substrat
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
FR2910702B1 (fr) 2006-12-26 2009-04-03 Soitec Silicon On Insulator Procede de fabrication d'un substrat mixte
FR2922359B1 (fr) * 2007-10-12 2009-12-18 Commissariat Energie Atomique Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire
FR2926748B1 (fr) 2008-01-25 2010-04-02 Commissariat Energie Atomique Objet muni d'un element graphique reporte sur un support et procede de realisation d'un tel objet.
JP5277975B2 (ja) * 2009-01-14 2013-08-28 株式会社村田製作所 複合基板の製造方法
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
FR2942674B1 (fr) * 2009-02-27 2011-12-16 Commissariat Energie Atomique Procede d'elaboration d'un substrat hybride par recristallisation partielle d'une couche mixte
FR2946435B1 (fr) 2009-06-04 2017-09-29 Commissariat Energie Atomique Procede de fabrication d'images colorees avec une resolution micronique enfouies dans un support tres robuste et tres perenne
FR2947098A1 (fr) * 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
JP5359615B2 (ja) * 2009-07-02 2013-12-04 株式会社村田製作所 複合基板の製造方法
WO2012015022A1 (ja) * 2010-07-30 2012-02-02 京セラ株式会社 複合基板、電子部品、ならびに複合基板および電子部品の製造方法
US8936996B2 (en) * 2010-12-02 2015-01-20 International Business Machines Corporation Structure and method for topography free SOI integration
US9481566B2 (en) 2012-07-31 2016-11-01 Soitec Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices
KR102007258B1 (ko) * 2012-11-21 2019-08-05 삼성전자주식회사 광전 집적회로 기판의 제조방법
FR3076292B1 (fr) * 2017-12-28 2020-01-03 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de transfert d'une couche utile sur un substrat support
FR3096173B1 (fr) * 2019-05-15 2021-05-28 Commissariat Energie Atomique Procédé d'auto-assemblage avec collage moléculaire hybride
FR3108788B1 (fr) * 2020-03-24 2026-01-23 Soitec Silicon On Insulator Procédé de fabrication d’une structure piézoélectrique pour dispositif radiofréquence et pouvant servir pour le transfert d’une couche piézoélectrique, et procédé de transfert d’une telle couche piézoélectrique

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US5138422A (en) * 1987-10-27 1992-08-11 Nippondenso Co., Ltd. Semiconductor device which includes multiple isolated semiconductor segments on one chip
JP2621325B2 (ja) * 1988-04-11 1997-06-18 富士通株式会社 Ｓｏｉ基板及びその製造方法
JPH043909A (ja) * 1990-04-20 1992-01-08 Fujitsu Ltd 半導体基板の張合わせ方法
JPH0429353A (ja) * 1990-05-24 1992-01-31 Sharp Corp 半導体装置
JPH06216136A (ja) * 1993-01-13 1994-08-05 Kawasaki Steel Corp 半導体基板およびその製造方法
JPH06334028A (ja) * 1993-05-25 1994-12-02 Nippondenso Co Ltd 誘電体分離基板の製造方法
TW289837B (de) * 1994-01-18 1996-11-01 Hwelett Packard Co
JP2624186B2 (ja) * 1994-07-29 1997-06-25 日本電気株式会社 貼り合わせシリコン基板の製造方法
US5661422A (en) * 1995-12-12 1997-08-26 Analog Devices, Inc. High speed saturation prevention for saturable circuit elements
JP3216535B2 (ja) * 1996-08-30 2001-10-09 日本電気株式会社 Ｓｏｉ基板およびその製造方法
JP3114643B2 (ja) 1997-02-20 2000-12-04 日本電気株式会社 半導体基板の構造および製造方法
US6013954A (en) * 1997-03-31 2000-01-11 Nec Corporation Semiconductor wafer having distortion-free alignment regions
US6054369A (en) * 1997-06-30 2000-04-25 Intersil Corporation Lifetime control for semiconductor devices
JP2000223679A (ja) * 1999-01-27 2000-08-11 Sharp Corp 半導体基板及びその製造方法
JP2001196566A (ja) * 2000-01-07 2001-07-19 Sony Corp 半導体基板およびその製造方法
FR2819099B1 (fr) * 2000-12-28 2003-09-26 Commissariat Energie Atomique Procede de realisation d'une structure empilee
FR2876219B1 (fr) * 2004-10-06 2006-11-24 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.
FR2876220B1 (fr) * 2004-10-06 2007-09-28 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.

Also Published As

Publication number Publication date
WO2004059711A1 (fr) 2004-07-15
FR2850487A1 (fr) 2004-07-30
US20060166461A1 (en) 2006-07-27
JP5188672B2 (ja) 2013-04-24
FR2850487B1 (fr) 2005-12-09
JP2006512754A (ja) 2006-04-13
US7494897B2 (en) 2009-02-24
EP1576658A1 (de) 2005-09-21
DE60326005D1 (de) 2009-03-12
EP1576658B1 (de) 2009-01-21

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