ATE455366T1 - Verfahren zur herstellung eines halbleitersubstrats mit einer schichtstruktur von aktivierten dotierungsstoffen - Google Patents

Verfahren zur herstellung eines halbleitersubstrats mit einer schichtstruktur von aktivierten dotierungsstoffen

Info

Publication number
ATE455366T1
ATE455366T1 AT03447259T AT03447259T ATE455366T1 AT E455366 T1 ATE455366 T1 AT E455366T1 AT 03447259 T AT03447259 T AT 03447259T AT 03447259 T AT03447259 T AT 03447259T AT E455366 T1 ATE455366 T1 AT E455366T1
Authority
AT
Austria
Prior art keywords
dopant
region
semiconductor substrate
thin layer
producing
Prior art date
Application number
AT03447259T
Other languages
English (en)
Inventor
Radu C Surdeanu
Original Assignee
Imec
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imec, Nxp Bv filed Critical Imec
Application granted granted Critical
Publication of ATE455366T1 publication Critical patent/ATE455366T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/916—Autodoping control or utilization

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
AT03447259T 2003-10-17 2003-10-17 Verfahren zur herstellung eines halbleitersubstrats mit einer schichtstruktur von aktivierten dotierungsstoffen ATE455366T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03447259A EP1524684B1 (de) 2003-10-17 2003-10-17 Verfahren zur Herstellung eines Halbleitersubstrats mit einer Schichtstruktur von aktivierten Dotierungsstoffen

Publications (1)

Publication Number Publication Date
ATE455366T1 true ATE455366T1 (de) 2010-01-15

Family

ID=34354656

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03447259T ATE455366T1 (de) 2003-10-17 2003-10-17 Verfahren zur herstellung eines halbleitersubstrats mit einer schichtstruktur von aktivierten dotierungsstoffen

Country Status (7)

Country Link
US (2) US7214592B2 (de)
EP (1) EP1524684B1 (de)
JP (1) JP4750400B2 (de)
CN (1) CN100442444C (de)
AT (1) ATE455366T1 (de)
DE (1) DE60330965D1 (de)
TW (1) TWI256079B (de)

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JP2006245338A (ja) * 2005-03-03 2006-09-14 Nec Electronics Corp 電界効果型トランジスタの製造方法
US7786003B1 (en) * 2005-05-25 2010-08-31 Advanced Micro Devices, Inc. Buried silicide local interconnect with sidewall spacers and method for making the same
US20070037326A1 (en) * 2005-08-09 2007-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow source/drain regions for CMOS transistors
US20070212861A1 (en) * 2006-03-07 2007-09-13 International Business Machines Corporation Laser surface annealing of antimony doped amorphized semiconductor region
US20070212859A1 (en) 2006-03-08 2007-09-13 Paul Carey Method of thermal processing structures formed on a substrate
JP5558006B2 (ja) * 2006-03-08 2014-07-23 アプライド マテリアルズ インコーポレイテッド 基板に形成された熱処理構造用の方法および装置
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US7718513B2 (en) * 2007-04-13 2010-05-18 International Business Machines Corporation Forming silicided gate and contacts from polysilicon germanium and structure formed
US8198547B2 (en) 2009-07-23 2012-06-12 Lexmark International, Inc. Z-directed pass-through components for printed circuit boards
US8012843B2 (en) * 2009-08-07 2011-09-06 Varian Semiconductor Equipment Associates, Inc. Optimized halo or pocket cold implants
US9078374B2 (en) * 2011-08-31 2015-07-07 Lexmark International, Inc. Screening process for manufacturing a Z-directed component for a printed circuit board
US9009954B2 (en) 2011-08-31 2015-04-21 Lexmark International, Inc. Process for manufacturing a Z-directed component for a printed circuit board using a sacrificial constraining material
US8943684B2 (en) 2011-08-31 2015-02-03 Lexmark International, Inc. Continuous extrusion process for manufacturing a Z-directed component for a printed circuit board
WO2013095340A1 (en) * 2011-12-19 2013-06-27 Intel Corporation Pulsed laser anneal process for transistors with partial melt of a raised source-drain

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JPH03131020A (ja) * 1989-10-16 1991-06-04 Sanyo Electric Co Ltd 半導体装置の製造方法
JPH0492477A (ja) * 1990-08-08 1992-03-25 Hitachi Ltd 可変容量ダイオードの製造方法
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DE10058031B4 (de) * 2000-11-23 2007-11-22 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Bildung leicht dotierter Halogebiete und Erweiterungsgebiete in einem Halbleiterbauelement
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Also Published As

Publication number Publication date
US7214592B2 (en) 2007-05-08
DE60330965D1 (de) 2010-03-04
TW200515489A (en) 2005-05-01
EP1524684B1 (de) 2010-01-13
CN1645568A (zh) 2005-07-27
US20050112831A1 (en) 2005-05-26
US20070267660A1 (en) 2007-11-22
TWI256079B (en) 2006-06-01
EP1524684A1 (de) 2005-04-20
JP4750400B2 (ja) 2011-08-17
JP2005129930A (ja) 2005-05-19
CN100442444C (zh) 2008-12-10

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