ATE456156T1 - Methode und vorrichtung zum messen von parametern eines elektronischen bauelementes - Google Patents

Methode und vorrichtung zum messen von parametern eines elektronischen bauelementes

Info

Publication number
ATE456156T1
ATE456156T1 AT01969473T AT01969473T ATE456156T1 AT E456156 T1 ATE456156 T1 AT E456156T1 AT 01969473 T AT01969473 T AT 01969473T AT 01969473 T AT01969473 T AT 01969473T AT E456156 T1 ATE456156 T1 AT E456156T1
Authority
AT
Austria
Prior art keywords
electronic component
measuring parameters
substrate
drain
circuit
Prior art date
Application number
AT01969473T
Other languages
English (en)
Inventor
Laurence Bourdillon
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE456156T1 publication Critical patent/ATE456156T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6717—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)
AT01969473T 2000-08-07 2001-07-20 Methode und vorrichtung zum messen von parametern eines elektronischen bauelementes ATE456156T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/633,761 US6433573B1 (en) 2000-08-07 2000-08-07 Method and apparatus for measuring parameters of an electronic device
PCT/EP2001/008474 WO2002013259A2 (en) 2000-08-07 2001-07-20 Method and apparatus for measuring parameters of an electronic device

Publications (1)

Publication Number Publication Date
ATE456156T1 true ATE456156T1 (de) 2010-02-15

Family

ID=24541027

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01969473T ATE456156T1 (de) 2000-08-07 2001-07-20 Methode und vorrichtung zum messen von parametern eines elektronischen bauelementes

Country Status (8)

Country Link
US (2) US6433573B1 (de)
EP (1) EP1309995B1 (de)
JP (1) JP2004506217A (de)
KR (1) KR100803493B1 (de)
CN (1) CN1240140C (de)
AT (1) ATE456156T1 (de)
DE (1) DE60141144D1 (de)
WO (1) WO2002013259A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006071292A (ja) * 2004-08-31 2006-03-16 Sanyo Electric Co Ltd 回路装置の製造方法
US7741823B2 (en) * 2007-01-29 2010-06-22 Agere Systems Inc. Linear voltage regulator with improved large transient response
US8631371B2 (en) 2011-06-29 2014-01-14 International Business Machines Corporation Method, system and program storage device for modeling the capacitance associated with a diffusion region of a silicon-on-insulator device
CN102866303A (zh) * 2011-07-05 2013-01-09 中国科学院微电子研究所 纳米器件沟道超薄栅介质电容测试方法
CN103969544B (zh) * 2014-03-04 2018-02-16 深圳博用科技有限公司 一种集成电路高压引脚连通性测试方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61280651A (ja) * 1985-05-24 1986-12-11 Fujitsu Ltd 半導体記憶装置
US4864374A (en) 1987-11-30 1989-09-05 Texas Instruments Incorporated Two-transistor dram cell with high alpha particle immunity
JP2698645B2 (ja) 1988-05-25 1998-01-19 株式会社東芝 Ｍｏｓｆｅｔ
US5382818A (en) 1993-12-08 1995-01-17 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode
KR0135804B1 (ko) * 1994-06-13 1998-04-24 김광호 실리콘 온 인슐레이터(soi) 트랜지스터
JP3732914B2 (ja) 1997-02-28 2006-01-11 株式会社ルネサステクノロジ 半導体装置
US6188234B1 (en) * 1999-01-07 2001-02-13 International Business Machines Corporation Method of determining dielectric time-to-breakdown

Also Published As

Publication number Publication date
US6876036B2 (en) 2005-04-05
EP1309995A2 (de) 2003-05-14
US6433573B1 (en) 2002-08-13
CN1240140C (zh) 2006-02-01
CN1421047A (zh) 2003-05-28
WO2002013259A3 (en) 2002-04-11
EP1309995B1 (de) 2010-01-20
DE60141144D1 (de) 2010-03-11
JP2004506217A (ja) 2004-02-26
US20030016047A1 (en) 2003-01-23
KR20020047212A (ko) 2002-06-21
KR100803493B1 (ko) 2008-02-14
WO2002013259A2 (en) 2002-02-14

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Legal Events

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