ATE467908T1 - Verfahren zur herstellung eines doppelgate- transistors - Google Patents

Verfahren zur herstellung eines doppelgate- transistors

Info

Publication number
ATE467908T1
ATE467908T1 AT07805282T AT07805282T ATE467908T1 AT E467908 T1 ATE467908 T1 AT E467908T1 AT 07805282 T AT07805282 T AT 07805282T AT 07805282 T AT07805282 T AT 07805282T AT E467908 T1 ATE467908 T1 AT E467908T1
Authority
AT
Austria
Prior art keywords
semiconductor layer
amorphous
gate transistor
channel
providing
Prior art date
Application number
AT07805282T
Other languages
English (en)
Inventor
Bartlomiej Pawlak
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE467908T1 publication Critical patent/ATE467908T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H10P14/3804—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation-inhibiting elements

Landscapes

  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
AT07805282T 2006-08-04 2007-08-01 Verfahren zur herstellung eines doppelgate- transistors ATE467908T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06118448 2006-08-04
PCT/IB2007/053036 WO2008015649A1 (en) 2006-08-04 2007-08-01 Method of manufacturing a double gate transistor

Publications (1)

Publication Number Publication Date
ATE467908T1 true ATE467908T1 (de) 2010-05-15

Family

ID=38792440

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07805282T ATE467908T1 (de) 2006-08-04 2007-08-01 Verfahren zur herstellung eines doppelgate- transistors

Country Status (6)

Country Link
US (1) US8183116B2 (de)
EP (1) EP2050140B1 (de)
CN (1) CN101501861B (de)
AT (1) ATE467908T1 (de)
DE (1) DE602007006507D1 (de)
WO (1) WO2008015649A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10043676B2 (en) * 2015-10-15 2018-08-07 Vishay General Semiconductor Llc Local semiconductor wafer thinning
CN108767011A (zh) * 2018-04-28 2018-11-06 南京邮电大学 一种双栅mosfet结构

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2595525B2 (ja) * 1987-04-10 1997-04-02 ソニー株式会社 半導体薄膜の形成方法
US6593192B2 (en) * 2001-04-27 2003-07-15 Micron Technology, Inc. Method of forming a dual-gated semiconductor-on-insulator device
US6661044B2 (en) * 2001-10-22 2003-12-09 Winbond Electronics Corp. Method of manufacturing MOSEFT and structure thereof
JP2003318405A (ja) * 2002-04-25 2003-11-07 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2003332582A (ja) * 2002-05-13 2003-11-21 Toshiba Corp 半導体装置及びその製造方法
CN1224087C (zh) * 2002-08-26 2005-10-19 中国科学院微电子中心 凹槽平面双栅结构mos器件及制造方法
JP4178296B2 (ja) * 2003-03-28 2008-11-12 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
US6838329B2 (en) * 2003-03-31 2005-01-04 Intel Corporation High concentration indium fluorine retrograde wells
US6936505B2 (en) * 2003-05-20 2005-08-30 Intel Corporation Method of forming a shallow junction
US7019342B2 (en) * 2003-07-03 2006-03-28 American Semiconductor, Inc. Double-gated transistor circuit
US7018873B2 (en) * 2003-08-13 2006-03-28 International Business Machines Corporation Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate
JP2007504660A (ja) * 2003-09-03 2007-03-01 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ ダブルゲート電界効果トランジスタ装置を製造する方法、及びそのようなダブルゲート電界効果トランジスタ装置
US7923782B2 (en) * 2004-02-27 2011-04-12 International Business Machines Corporation Hybrid SOI/bulk semiconductor transistors
GB0411621D0 (en) * 2004-05-25 2004-06-30 Koninkl Philips Electronics Nv Dual gate semiconductor device

Also Published As

Publication number Publication date
EP2050140B1 (de) 2010-05-12
CN101501861B (zh) 2010-12-08
WO2008015649A1 (en) 2008-02-07
US20100237351A1 (en) 2010-09-23
EP2050140A1 (de) 2009-04-22
US8183116B2 (en) 2012-05-22
DE602007006507D1 (de) 2010-06-24
CN101501861A (zh) 2009-08-05

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Legal Events

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