ATE502394T1 - Verfahren zur herstellung von abtrennbaren substraten - Google Patents

Verfahren zur herstellung von abtrennbaren substraten

Info

Publication number
ATE502394T1
ATE502394T1 AT03809826T AT03809826T ATE502394T1 AT E502394 T1 ATE502394 T1 AT E502394T1 AT 03809826 T AT03809826 T AT 03809826T AT 03809826 T AT03809826 T AT 03809826T AT E502394 T1 ATE502394 T1 AT E502394T1
Authority
AT
Austria
Prior art keywords
substrates
producing separable
layers
separable substrates
condition adjustment
Prior art date
Application number
AT03809826T
Other languages
English (en)
Inventor
Olivier Rayssac
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE502394T1 publication Critical patent/ATE502394T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H10P70/12—Cleaning before device manufacture, i.e. Begin-Of-Line process by dry cleaning only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Drying Of Semiconductors (AREA)
  • Manufacturing Of Electric Cables (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Laminated Bodies (AREA)
  • Treatments Of Macromolecular Shaped Articles (AREA)
  • Inorganic Insulating Materials (AREA)
  • Addition Polymer Or Copolymer, Post-Treatments, Or Chemical Modifications (AREA)
  • Silicon Compounds (AREA)
  • Glass Compositions (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Micromachines (AREA)
AT03809826T 2002-10-30 2003-10-29 Verfahren zur herstellung von abtrennbaren substraten ATE502394T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0213582A FR2846788B1 (fr) 2002-10-30 2002-10-30 Procede de fabrication de substrats demontables
PCT/IB2003/005296 WO2004040476A1 (en) 2002-10-30 2003-10-29 Manufacturing process of detachable substrates

Publications (1)

Publication Number Publication Date
ATE502394T1 true ATE502394T1 (de) 2011-04-15

Family

ID=32104308

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03809826T ATE502394T1 (de) 2002-10-30 2003-10-29 Verfahren zur herstellung von abtrennbaren substraten

Country Status (9)

Country Link
US (1) US7056809B2 (de)
EP (1) EP1556888B1 (de)
JP (1) JP4541150B2 (de)
AT (1) ATE502394T1 (de)
AU (1) AU2003276623A1 (de)
DE (1) DE60336410D1 (de)
FR (1) FR2846788B1 (de)
TW (1) TWI281187B (de)
WO (1) WO2004040476A1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7166524B2 (en) * 2000-08-11 2007-01-23 Applied Materials, Inc. Method for ion implanting insulator material to reduce dielectric constant
US7223676B2 (en) * 2002-06-05 2007-05-29 Applied Materials, Inc. Very low temperature CVD process with independently variable conformality, stress and composition of the CVD layer
US7294563B2 (en) * 2000-08-10 2007-11-13 Applied Materials, Inc. Semiconductor on insulator vertical transistor fabrication and doping process
US6939434B2 (en) * 2000-08-11 2005-09-06 Applied Materials, Inc. Externally excited torroidal plasma source with magnetic control of ion distribution
US6893907B2 (en) * 2002-06-05 2005-05-17 Applied Materials, Inc. Fabrication of silicon-on-insulator structure using plasma immersion ion implantation
US20070042580A1 (en) * 2000-08-10 2007-02-22 Amir Al-Bayati Ion implanted insulator material with reduced dielectric constant
US7465478B2 (en) * 2000-08-11 2008-12-16 Applied Materials, Inc. Plasma immersion ion implantation process
US7183177B2 (en) * 2000-08-11 2007-02-27 Applied Materials, Inc. Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement
US7288491B2 (en) * 2000-08-11 2007-10-30 Applied Materials, Inc. Plasma immersion ion implantation process
US7094670B2 (en) * 2000-08-11 2006-08-22 Applied Materials, Inc. Plasma immersion ion implantation process
US7320734B2 (en) * 2000-08-11 2008-01-22 Applied Materials, Inc. Plasma immersion ion implantation system including a plasma source having low dissociation and low minimum plasma voltage
US20050230047A1 (en) * 2000-08-11 2005-10-20 Applied Materials, Inc. Plasma immersion ion implantation apparatus
US7303982B2 (en) * 2000-08-11 2007-12-04 Applied Materials, Inc. Plasma immersion ion implantation process using an inductively coupled plasma source having low dissociation and low minimum plasma voltage
US7137354B2 (en) * 2000-08-11 2006-11-21 Applied Materials, Inc. Plasma immersion ion implantation apparatus including a plasma source having low dissociation and low minimum plasma voltage
US7037813B2 (en) * 2000-08-11 2006-05-02 Applied Materials, Inc. Plasma immersion ion implantation process using a capacitively coupled plasma source having low dissociation and low minimum plasma voltage
US7341330B2 (en) 2005-02-28 2008-03-11 Silverbrook Research Pty Ltd Substrates adapted for adhesive bonding
US7425052B2 (en) 2005-02-28 2008-09-16 Silverbrook Research Pty Ltd Printhead assembly having improved adhesive bond strength
US7468284B2 (en) 2005-02-28 2008-12-23 Silverbrook Research Pty Ltd Method of bonding substrates
JP4225510B2 (ja) * 2005-07-06 2009-02-18 昭和電工株式会社 化合物半導体発光ダイオードおよびその製造方法
US20070023850A1 (en) * 2005-07-30 2007-02-01 Chien-Hua Chen Bonding surfaces together via plasma treatment on both surfaces with wet treatment on only one surface
EP2128891B1 (de) 2007-02-28 2015-09-02 Shin-Etsu Chemical Co., Ltd. Prozess zum herstellen eines laminierten substrats
JP5143477B2 (ja) * 2007-05-31 2013-02-13 信越化学工業株式会社 Ｓｏｉウエーハの製造方法
KR101031010B1 (ko) * 2008-10-29 2011-04-25 삼성메디슨 주식회사 피씨비 및 이를 구비하는 프로브
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
US10825685B2 (en) * 2010-08-23 2020-11-03 Exogenesis Corporation Method for neutral beam processing based on gas cluster ion beam technology and articles produced thereby
JP6042658B2 (ja) * 2011-09-07 2016-12-14 トヨタ自動車株式会社 ＳｉＣ半導体素子の製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6271271A (ja) * 1985-09-24 1987-04-01 Sharp Corp 炭化珪素半導体の電極構造
US5354695A (en) * 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
AU9296098A (en) * 1997-08-29 1999-03-16 Sharon N. Farrens In situ plasma wafer bonding method
US6153495A (en) * 1998-03-09 2000-11-28 Intersil Corporation Advanced methods for making semiconductor devices by low temperature direct bonding
DE19818962A1 (de) * 1998-04-28 1999-11-04 Degussa Verfahren zum Verbinden zweier Festkörper und das so hergestellte Bauelement
US6375790B1 (en) * 1999-07-19 2002-04-23 Epion Corporation Adaptive GCIB for smoothing surfaces
FR2797347B1 (fr) * 1999-08-04 2001-11-23 Commissariat Energie Atomique Procede de transfert d'une couche mince comportant une etape de surfragililisation
US6902987B1 (en) * 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
WO2002005315A2 (en) * 2000-07-10 2002-01-17 Epion Corporation System and method for improving thin films by gas cluster ion be am processing
FR2823599B1 (fr) 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
FR2823596B1 (fr) 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
JP3881562B2 (ja) * 2002-02-22 2007-02-14 三井造船株式会社 ＳｉＣモニタウェハ製造方法
TWI233154B (en) * 2002-12-06 2005-05-21 Soitec Silicon On Insulator Method for recycling a substrate

Also Published As

Publication number Publication date
WO2004040476A9 (en) 2004-06-24
JP2006505122A (ja) 2006-02-09
TW200421417A (en) 2004-10-16
WO2004040476A1 (en) 2004-05-13
AU2003276623A8 (en) 2004-05-25
AU2003276623A1 (en) 2004-05-25
US7056809B2 (en) 2006-06-06
EP1556888A1 (de) 2005-07-27
US20040092084A1 (en) 2004-05-13
TWI281187B (en) 2007-05-11
DE60336410D1 (de) 2011-04-28
JP4541150B2 (ja) 2010-09-08
FR2846788A1 (fr) 2004-05-07
FR2846788B1 (fr) 2005-06-17
EP1556888B1 (de) 2011-03-16

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