ATE535020T1 - Verfahren zur herstellung einer halbleiteranordnung mit übergang - Google Patents

Verfahren zur herstellung einer halbleiteranordnung mit übergang

Info

Publication number
ATE535020T1
ATE535020T1 AT06005896T AT06005896T ATE535020T1 AT E535020 T1 ATE535020 T1 AT E535020T1 AT 06005896 T AT06005896 T AT 06005896T AT 06005896 T AT06005896 T AT 06005896T AT E535020 T1 ATE535020 T1 AT E535020T1
Authority
AT
Austria
Prior art keywords
forming
resistance layer
region
junction
gate region
Prior art date
Application number
AT06005896T
Other languages
English (en)
Inventor
Ken-Ichi Nonaka
Hideki Hashimoto
Seiichi Yokoyama
Kensuke Iwanaga
Yoshimitsu Saito
Hiroaki Iwakuro
Masaaki Shimizu
Yusuke Fukuda
Koichi Nishikawa
Yusuke Maeyama
Original Assignee
Honda Motor Co Ltd
Shindengen Electric Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honda Motor Co Ltd, Shindengen Electric Mfg filed Critical Honda Motor Co Ltd
Application granted granted Critical
Publication of ATE535020T1 publication Critical patent/ATE535020T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/202—FETs having static field-induced regions, e.g. static-induction transistors [SIT] or permeable base transistors [PBT]

Landscapes

  • Junction Field-Effect Transistors (AREA)
AT06005896T 2005-03-23 2006-03-22 Verfahren zur herstellung einer halbleiteranordnung mit übergang ATE535020T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005084671A JP4996828B2 (ja) 2005-03-23 2005-03-23 接合型半導体装置の製造方法

Publications (1)

Publication Number Publication Date
ATE535020T1 true ATE535020T1 (de) 2011-12-15

Family

ID=36607549

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06005896T ATE535020T1 (de) 2005-03-23 2006-03-22 Verfahren zur herstellung einer halbleiteranordnung mit übergang

Country Status (6)

Country Link
US (1) US7544552B2 (de)
EP (1) EP1705712B1 (de)
JP (1) JP4996828B2 (de)
KR (1) KR20060103140A (de)
CN (1) CN100499051C (de)
AT (1) ATE535020T1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2325872A4 (de) * 2008-08-26 2013-11-20 Honda Motor Co Ltd Bipolares halbleiterbauelement und herstellungsverfahren dafür
WO2010024239A1 (ja) * 2008-08-26 2010-03-04 本田技研工業株式会社 接合型半導体装置およびその製造方法
JP2011091179A (ja) * 2009-10-22 2011-05-06 Honda Motor Co Ltd バイポーラ型半導体装置およびその製造方法
JP5607947B2 (ja) 2010-02-17 2014-10-15 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8829574B2 (en) * 2011-12-22 2014-09-09 Avogy, Inc. Method and system for a GaN vertical JFET with self-aligned source and gate
US8723178B2 (en) * 2012-01-20 2014-05-13 Monolithic Power Systems, Inc. Integrated field effect transistors with high voltage drain sensing
US8841708B2 (en) 2012-05-10 2014-09-23 Avogy, Inc. Method and system for a GAN vertical JFET with self-aligned source metallization
US8716078B2 (en) * 2012-05-10 2014-05-06 Avogy, Inc. Method and system for a gallium nitride vertical JFET with self-aligned gate metallization
JP6073719B2 (ja) * 2013-03-21 2017-02-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
JP6138619B2 (ja) * 2013-07-30 2017-05-31 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
WO2015052782A1 (ja) * 2013-10-08 2015-04-16 新電元工業株式会社 炭化珪素半導体装置の製造方法
TWI753633B (zh) * 2020-10-30 2022-01-21 台灣奈米碳素股份有限公司 利用電漿輔助原子層沉積技術製造的半導體裝置及其方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0770474B2 (ja) * 1985-02-08 1995-07-31 株式会社東芝 化合物半導体装置の製造方法
JP2794369B2 (ja) 1992-12-11 1998-09-03 キヤノン株式会社 液晶素子
US5554561A (en) * 1993-04-30 1996-09-10 Texas Instruments Incorporated Epitaxial overgrowth method
JP3789949B2 (ja) * 1994-03-07 2006-06-28 本田技研工業株式会社 半導体装置
US5705830A (en) * 1996-09-05 1998-01-06 Northrop Grumman Corporation Static induction transistors
EP1199099A1 (de) * 2000-10-19 2002-04-24 Amersham Biosciences AB Reaktor
JP3692063B2 (ja) * 2001-03-28 2005-09-07 株式会社東芝 半導体装置及びその製造方法
JP4153811B2 (ja) * 2002-03-25 2008-09-24 株式会社東芝 高耐圧半導体装置及びその製造方法
JP2004134547A (ja) 2002-10-10 2004-04-30 Hitachi Ltd 半導体装置
JP4777676B2 (ja) * 2005-03-23 2011-09-21 本田技研工業株式会社 接合型半導体装置および接合型半導体装置の製造方法

Also Published As

Publication number Publication date
US20060216879A1 (en) 2006-09-28
JP4996828B2 (ja) 2012-08-08
EP1705712B1 (de) 2011-11-23
EP1705712A1 (de) 2006-09-27
US7544552B2 (en) 2009-06-09
CN1838390A (zh) 2006-09-27
KR20060103140A (ko) 2006-09-28
JP2006269679A (ja) 2006-10-05
CN100499051C (zh) 2009-06-10

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