ATE545909T1 - Multiprozessorsystem mit gemeinsamem adressenübersetzungspufferspeicher - Google Patents
Multiprozessorsystem mit gemeinsamem adressenübersetzungspufferspeicherInfo
- Publication number
- ATE545909T1 ATE545909T1 AT01401386T AT01401386T ATE545909T1 AT E545909 T1 ATE545909 T1 AT E545909T1 AT 01401386 T AT01401386 T AT 01401386T AT 01401386 T AT01401386 T AT 01401386T AT E545909 T1 ATE545909 T1 AT E545909T1
- Authority
- AT
- Austria
- Prior art keywords
- multiprocessor system
- tlb
- buffer memory
- address translation
- translation
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/68—Details of translation look-aside buffer [TLB]
- G06F2212/681—Multi-level TLB, e.g. microTLB and main TLB
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP01401386A EP1262876B1 (de) | 2001-05-28 | 2001-05-28 | Multiprozessorsystem mit gemeinsamem Adressenübersetzungspufferspeicher |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE545909T1 true ATE545909T1 (de) | 2012-03-15 |
Family
ID=8182749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT01401386T ATE545909T1 (de) | 2001-05-28 | 2001-05-28 | Multiprozessorsystem mit gemeinsamem adressenübersetzungspufferspeicher |
Country Status (2)
| Country | Link |
|---|---|
| EP (1) | EP1262876B1 (de) |
| AT (1) | ATE545909T1 (de) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2529394A (en) | 2014-08-14 | 2016-02-24 | Ibm | Multiprocessor computer system |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4481573A (en) * | 1980-11-17 | 1984-11-06 | Hitachi, Ltd. | Shared virtual address translation unit for a multiprocessor system |
| US4774653A (en) | 1985-08-07 | 1988-09-27 | Hewlett-Packard Company | Hybrid hardware/software method and apparatus for virtual memory address translation using primary and secondary translation buffers |
| JPH087719B2 (ja) | 1989-02-10 | 1996-01-29 | 日本電気株式会社 | 情報処理システム |
| US5479627A (en) * | 1993-09-08 | 1995-12-26 | Sun Microsystems, Inc. | Virtual address to physical address translation cache that supports multiple page sizes |
-
2001
- 2001-05-28 AT AT01401386T patent/ATE545909T1/de active
- 2001-05-28 EP EP01401386A patent/EP1262876B1/de not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP1262876A1 (de) | 2002-12-04 |
| EP1262876B1 (de) | 2012-02-15 |
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