ATE98815T1 - Verfahren zum herstellen eines komplementaeren bicmos-transistors mit isoliertem vertikalem pnp- transistor. - Google Patents

Verfahren zum herstellen eines komplementaeren bicmos-transistors mit isoliertem vertikalem pnp- transistor.

Info

Publication number
ATE98815T1
ATE98815T1 AT89300019T AT89300019T ATE98815T1 AT E98815 T1 ATE98815 T1 AT E98815T1 AT 89300019 T AT89300019 T AT 89300019T AT 89300019 T AT89300019 T AT 89300019T AT E98815 T1 ATE98815 T1 AT E98815T1
Authority
AT
Austria
Prior art keywords
pnp transistor
transistor
implant
high energy
steps
Prior art date
Application number
AT89300019T
Other languages
English (en)
Inventor
Kola Nirmal Ratnakumar
Original Assignee
Exar Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Exar Corp filed Critical Exar Corp
Application granted granted Critical
Publication of ATE98815T1 publication Critical patent/ATE98815T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0119—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs
    • H10D84/0121—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs the complementary BJTs being vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/225—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of a molecular ion, e.g. decaborane

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
AT89300019T 1988-01-21 1989-01-04 Verfahren zum herstellen eines komplementaeren bicmos-transistors mit isoliertem vertikalem pnp- transistor. ATE98815T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14693488A 1988-01-21 1988-01-21
EP89300019A EP0325342B1 (de) 1988-01-21 1989-01-04 Verfahren zum Herstellen eines komplementären BICMOS-Transistors mit isoliertem vertikalem PNP-Transistor

Publications (1)

Publication Number Publication Date
ATE98815T1 true ATE98815T1 (de) 1994-01-15

Family

ID=22519636

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89300019T ATE98815T1 (de) 1988-01-21 1989-01-04 Verfahren zum herstellen eines komplementaeren bicmos-transistors mit isoliertem vertikalem pnp- transistor.

Country Status (5)

Country Link
EP (1) EP0325342B1 (de)
JP (1) JPH0748530B2 (de)
KR (1) KR910009337B1 (de)
AT (1) ATE98815T1 (de)
DE (1) DE68911321T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940003589B1 (ko) * 1991-02-25 1994-04-25 삼성전자 주식회사 BiCMOS 소자의 제조 방법
DE4411869C2 (de) * 1994-04-06 1997-05-15 Siemens Ag Schaltungsanordnung mit einer integrierten Treiberschaltungsanordnung
RU2106039C1 (ru) * 1995-11-09 1998-02-27 Акционерное общество открытого типа "НИИМЭ и завод "Микрон" Способ изготовления бикмоп структур
RU2141148C1 (ru) * 1998-07-09 1999-11-10 Акционерное общество открытого типа "НИИМЭ и завод "Микрон" Способ изготовления бикмоп прибора
RU2141149C1 (ru) * 1998-07-09 1999-11-10 Акционерное общество открытого типа "Научно-исследовательский институт молекулярной электроники и завод "Микрон" Способ изготовления бикмоп структуры
DE19844531B4 (de) * 1998-09-29 2017-12-14 Prema Semiconductor Gmbh Verfahren zur Herstellung von Transistoren

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4637125A (en) * 1983-09-22 1987-01-20 Kabushiki Kaisha Toshiba Method for making a semiconductor integrated device including bipolar transistor and CMOS transistor
US4752589A (en) * 1985-12-17 1988-06-21 Siemens Aktiengesellschaft Process for the production of bipolar transistors and complementary MOS transistors on a common silicon substrate
US4737472A (en) * 1985-12-17 1988-04-12 Siemens Aktiengesellschaft Process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate

Also Published As

Publication number Publication date
EP0325342A2 (de) 1989-07-26
DE68911321D1 (de) 1994-01-27
JPH0748530B2 (ja) 1995-05-24
KR890012391A (ko) 1989-08-26
DE68911321T2 (de) 1994-07-07
EP0325342A3 (en) 1990-10-03
KR910009337B1 (ko) 1991-11-11
EP0325342B1 (de) 1993-12-15
JPH027462A (ja) 1990-01-11

Similar Documents

Publication Publication Date Title
JPS5685848A (en) Manufacture of bipolar integrated circuit
EP0949665A3 (de) Bipolarer Transistor mit hoher Geschwindigkeit und niedriger parasitärer Kapazität und Verfahren zur deren Herstellung
GB1262705A (en) Improvements relating to the fabrication of semiconductor devices
TW344885B (en) Integrated circuit, components thereof and manufacturing method
WO1986003334A3 (en) Semiconductors having shallow, hyperabrupt doped regions, and process for preparation thereof using ion implanted impurities
WO1988006804A3 (en) Low leakage cmos/insulator substrate devices and method of forming the same
JPS55151349A (en) Forming method of insulation isolating region
ATE98815T1 (de) Verfahren zum herstellen eines komplementaeren bicmos-transistors mit isoliertem vertikalem pnp- transistor.
EP0296627A3 (de) Verfahren zur Herstellung einer Halbleiteranordnung
SE9603608D0 (sv) A method for producing a region doped with boron in a SiC-layer
JPS5787119A (en) Manufacture of semiconductor device
KR890003026A (ko) 고속 고집적 반도체소자(BiCMOS)의 제조방법
US5244821A (en) Bipolar fabrication method
JP2001517366A (ja) Ｍｅｖ ｂｉｌｌｉ（ｂｕｒｉｅｄ ｉｍｐｌａｎｔｅｄ ｌａｙｅｒ ｆｏｒ ｌａｔｅｒａｌ ｉｓｏｌａｔｉｏｎ）と埋め込み層注入によるｃｍｏｓラッチアップの改善の方法
JP2998730B2 (ja) 三重ウェルを有する半導体素子の製造方法
JPS6437835A (en) Formation of layer of semiconductor device through ion implantation
JPS6428813A (en) Manufacture of semiconductor device
JPS57136358A (en) Integrated circuit device and manufacture thereof
JP2881833B2 (ja) 半導体装置の製造方法
US5312764A (en) Method of doping a semiconductor substrate
EP0385906A3 (de) Verfahren zur Herstellung eines lateralen PNP Transistors
Myers et al. Electronic Properties of Ion-Implanted Silicon Annealed with Microsecond Dye-Laser Pulses
JPS6386565A (ja) 半導体装置の製造方法
JPS6459952A (en) Manufacture of bicmos integrated circuit
JPS5624954A (en) Formation of buried layer

Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee