CA1120609A - Method for forming a narrow dimensioned mask opening on a silicon body - Google Patents

Method for forming a narrow dimensioned mask opening on a silicon body

Info

Publication number
CA1120609A
CA1120609A CA000336935A CA336935A CA1120609A CA 1120609 A CA1120609 A CA 1120609A CA 000336935 A CA000336935 A CA 000336935A CA 336935 A CA336935 A CA 336935A CA 1120609 A CA1120609 A CA 1120609A
Authority
CA
Canada
Prior art keywords
insulator
layer
silicon
forming
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000336935A
Other languages
English (en)
French (fr)
Inventor
Irving T. Ho
Jacob Riseman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1120609A publication Critical patent/CA1120609A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
    • H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/116—Oxidation, differential
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/141—Self-alignment coat gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Landscapes

  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
CA000336935A 1978-11-03 1979-10-03 Method for forming a narrow dimensioned mask opening on a silicon body Expired CA1120609A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US957,605 1978-11-03
US05/957,605 US4209349A (en) 1978-11-03 1978-11-03 Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching

Publications (1)

Publication Number Publication Date
CA1120609A true CA1120609A (en) 1982-03-23

Family

ID=25499844

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000336935A Expired CA1120609A (en) 1978-11-03 1979-10-03 Method for forming a narrow dimensioned mask opening on a silicon body

Country Status (6)

Country Link
US (1) US4209349A (2)
EP (1) EP0010624B1 (2)
JP (2) JPS5857902B2 (2)
CA (1) CA1120609A (2)
DE (1) DE2963174D1 (2)
IT (1) IT1164517B (2)

Families Citing this family (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4402761A (en) * 1978-12-15 1983-09-06 Raytheon Company Method of making self-aligned gate MOS device having small channel lengths
US4282646A (en) * 1979-08-20 1981-08-11 International Business Machines Corporation Method of making a transistor array
JPS5669844A (en) * 1979-11-10 1981-06-11 Toshiba Corp Manufacture of semiconductor device
US4271583A (en) * 1980-03-10 1981-06-09 Bell Telephone Laboratories, Incorporated Fabrication of semiconductor devices having planar recessed oxide isolation region
US4274909A (en) * 1980-03-17 1981-06-23 International Business Machines Corporation Method for forming ultra fine deep dielectric isolation
US5202574A (en) * 1980-05-02 1993-04-13 Texas Instruments Incorporated Semiconductor having improved interlevel conductor insulation
US4378630A (en) * 1980-05-05 1983-04-05 International Business Machines Corporation Process for fabricating a high performance PNP and NPN structure
US4322883A (en) * 1980-07-08 1982-04-06 International Business Machines Corporation Self-aligned metal process for integrated injection logic integrated circuits
US4378627A (en) * 1980-07-08 1983-04-05 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
US4513303A (en) * 1980-07-08 1985-04-23 International Business Machines Corporation Self-aligned metal field effect transistor integrated circuit
US4359816A (en) * 1980-07-08 1982-11-23 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits
US4758528A (en) * 1980-07-08 1988-07-19 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
US4488162A (en) * 1980-07-08 1984-12-11 International Business Machines Corporation Self-aligned metal field effect transistor integrated circuits using polycrystalline silicon gate electrodes
US4358340A (en) * 1980-07-14 1982-11-09 Texas Instruments Incorporated Submicron patterning without using submicron lithographic technique
US4394196A (en) * 1980-07-16 1983-07-19 Tokyo Shibaura Denki Kabushiki Kaisha Method of etching, refilling and etching dielectric grooves for isolating micron size device regions
JPS5743438A (en) * 1980-08-29 1982-03-11 Toshiba Corp Semiconductor device and manufacture thereof
US4356623A (en) * 1980-09-15 1982-11-02 Texas Instruments Incorporated Fabrication of submicron semiconductor devices
JPS5758356A (en) * 1980-09-26 1982-04-08 Toshiba Corp Manufacture of semiconductor device
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
JPS57112028A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Manufacture of semiconductor device
US4442589A (en) * 1981-03-05 1984-04-17 International Business Machines Corporation Method for manufacturing field effect transistors
US4743565A (en) * 1981-03-30 1988-05-10 International Business Machines Corporation Lateral device structures using self-aligned fabrication techniques
US4508579A (en) * 1981-03-30 1985-04-02 International Business Machines Corporation Lateral device structures using self-aligned fabrication techniques
US4688073A (en) * 1981-03-30 1987-08-18 Goth George R Lateral device structures using self-aligned fabrication techniques
US4333794A (en) * 1981-04-07 1982-06-08 International Business Machines Corporation Omission of thick Si3 N4 layers in ISA schemes
US4796069A (en) * 1981-05-13 1989-01-03 International Business Machines Corporation Schottky diode having limited area self-aligned guard ring and method for making same
US4691435A (en) * 1981-05-13 1987-09-08 International Business Machines Corporation Method for making Schottky diode having limited area self-aligned guard ring
JPS57199221A (en) * 1981-06-02 1982-12-07 Toshiba Corp Manufacture of semiconductor device
FR2508704B1 (fr) * 1981-06-26 1985-06-07 Thomson Csf Procede de fabrication de transistors bipolaires integres de tres petites dimensions
JPS5848936A (ja) * 1981-09-10 1983-03-23 Fujitsu Ltd 半導体装置の製造方法
JPS5871638A (ja) * 1981-10-26 1983-04-28 Hitachi Ltd エツチング方法
NL8105559A (nl) * 1981-12-10 1983-07-01 Philips Nv Werkwijze voor het aanbrengen van een smalle groef in een substraatgebied, in het bijzonder een halfgeleidersubstraatgebied.
US4553316A (en) * 1981-12-24 1985-11-19 Texas Instruments Incorporated Self-aligned gate method for making MESFET semiconductor
US4455738A (en) * 1981-12-24 1984-06-26 Texas Instruments Incorporated Self-aligned gate method for making MESFET semiconductor
US4424621A (en) 1981-12-30 1984-01-10 International Business Machines Corporation Method to fabricate stud structure for self-aligned metallization
US4430791A (en) * 1981-12-30 1984-02-14 International Business Machines Corporation Sub-micrometer channel length field effect transistor process
US4445267A (en) * 1981-12-30 1984-05-01 International Business Machines Corporation MOSFET Structure and process to form micrometer long source/drain spacing
US4419809A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
US4419810A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Self-aligned field effect transistor process
NL8105920A (nl) * 1981-12-31 1983-07-18 Philips Nv Halfgeleiderinrichting en werkwijze voor het vervaardigen van een dergelijke halfgeleiderinrichting.
DE3242113A1 (de) * 1982-11-13 1984-05-24 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren zur herstellung einer duennen dielektrischen isolation in einem siliciumhalbleiterkoerper
US4464212A (en) * 1982-12-13 1984-08-07 International Business Machines Corporation Method for making high sheet resistivity resistors
JPS6074477A (ja) * 1983-09-29 1985-04-26 Fujitsu Ltd 半導体装置及びその製造方法
US4636834A (en) * 1983-12-12 1987-01-13 International Business Machines Corporation Submicron FET structure and method of making
US4551906A (en) * 1983-12-12 1985-11-12 International Business Machines Corporation Method for making self-aligned lateral bipolar transistors
US4546535A (en) * 1983-12-12 1985-10-15 International Business Machines Corporation Method of making submicron FET structure
JPS60257676A (ja) * 1984-06-01 1985-12-19 Matsushita Electronics Corp 固体撮像装置
US4574469A (en) * 1984-09-14 1986-03-11 Motorola, Inc. Process for self-aligned buried layer, channel-stop, and isolation
US4662956A (en) * 1985-04-01 1987-05-05 Motorola, Inc. Method for prevention of autodoping of epitaxial layers
US4678537A (en) * 1985-05-23 1987-07-07 Sony Corporation Method of manufacturing semiconductor devices
US4648937A (en) * 1985-10-30 1987-03-10 International Business Machines Corporation Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer
US4654119A (en) * 1985-11-18 1987-03-31 International Business Machines Corporation Method for making submicron mask openings using sidewall and lift-off techniques
US4707218A (en) * 1986-10-28 1987-11-17 International Business Machines Corporation Lithographic image size reduction
US4933295A (en) * 1987-05-08 1990-06-12 Raytheon Company Method of forming a bipolar transistor having closely spaced device regions
US4818713A (en) * 1987-10-20 1989-04-04 American Telephone And Telegraph Company, At&T Bell Laboratories Techniques useful in fabricating semiconductor devices having submicron features
EP0313683A1 (en) * 1987-10-30 1989-05-03 International Business Machines Corporation Method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element
US4818714A (en) * 1987-12-02 1989-04-04 Advanced Micro Devices, Inc. Method of making a high performance MOS device having LDD regions with graded junctions
DE3879186D1 (de) * 1988-04-19 1993-04-15 Ibm Verfahren zur herstellung von integrierten halbleiterstrukturen welche feldeffekttransistoren mit kanallaengen im submikrometerbereich enthalten.
US4943537A (en) * 1988-06-23 1990-07-24 Dallas Semiconductor Corporation CMOS integrated circuit with reduced susceptibility to PMOS punchthrough
US5122474A (en) * 1988-06-23 1992-06-16 Dallas Semiconductor Corporation Method of fabricating a CMOS IC with reduced susceptibility to PMOS punchthrough
US4906588A (en) * 1988-06-23 1990-03-06 Dallas Semiconductor Corporation Enclosed buried channel transistor
US5015595A (en) * 1988-09-09 1991-05-14 Advanced Micro Devices, Inc. Method of making a high performance MOS device having both P- and N-LDD regions using single photoresist mask
DE3888184D1 (de) * 1988-11-17 1994-04-07 Ibm Verfahren zur Herstellung von Masken mit Strukturen im Submikrometerbereich.
EP0694959A3 (en) * 1989-07-03 1997-12-29 AT&T Corp. Trench etching in an integrated-circuit semiconductor device
US5004703A (en) * 1989-07-21 1991-04-02 Motorola Multiple trench semiconductor structure method
IT1231300B (it) * 1989-07-24 1991-11-28 Sgs Thomson Microelectronics Processo di definizione e realizzazione di una regione attivadi dimensioni molto ridotte in uno strato di materiale semiconduttore
US5106471A (en) * 1990-04-02 1992-04-21 Motorola, Inc. Reactive ion etch process for surface acoustic wave (SAW) device fabrication
US5071780A (en) * 1990-08-27 1991-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Reverse self-aligned transistor integrated circuit
US5175606A (en) * 1990-08-27 1992-12-29 Taiwan Semiconductor Manufacturing Company Reverse self-aligned BiMOS transistor integrated circuit
US5028557A (en) * 1990-08-27 1991-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a reverse self-aligned BIMOS transistor integrated circuit
US5235204A (en) * 1990-08-27 1993-08-10 Taiwan Semiconductor Manufacturing Company Reverse self-aligned transistor integrated circuit
JPH05315604A (ja) * 1992-05-13 1993-11-26 Matsushita Electron Corp 半導体装置の製造方法
US5432103A (en) * 1992-06-22 1995-07-11 National Semiconductor Corporation Method of making semiconductor ROM cell programmed using source mask
US6139483A (en) * 1993-07-27 2000-10-31 Texas Instruments Incorporated Method of forming lateral resonant tunneling devices
US5466615A (en) * 1993-08-19 1995-11-14 Taiwan Semiconductor Manufacturing Company Ltd. Silicon damage free process for double poly emitter and reverse MOS in BiCMOS application
US5618383A (en) * 1994-03-30 1997-04-08 Texas Instruments Incorporated Narrow lateral dimensioned microelectronic structures and method of forming the same
US5665997A (en) * 1994-03-31 1997-09-09 Texas Instruments Incorporated Grated landing area to eliminate sticking of micro-mechanical devices
US5460991A (en) * 1995-03-16 1995-10-24 United Microelectronics Corporation Method of making high coupling ratio flash EEPROM device
US5714039A (en) * 1995-10-04 1998-02-03 International Business Machines Corporation Method for making sub-lithographic images by etching the intersection of two spacers
CN1072392C (zh) * 1996-09-09 2001-10-03 美禄科技股份有限公司 高密度金属栅金属氧化物半导体的制造方法
US5804485A (en) * 1997-02-25 1998-09-08 Miracle Technology Co Ltd High density metal gate MOS fabrication process
US6306702B1 (en) 1999-08-24 2001-10-23 Advanced Micro Devices, Inc. Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length
US6540928B1 (en) 1999-09-10 2003-04-01 Unaxis Usa Inc. Magnetic pole fabrication process and device
US6547975B1 (en) 1999-10-29 2003-04-15 Unaxis Usa Inc. Magnetic pole fabrication process and device
US6413792B1 (en) 2000-04-24 2002-07-02 Eagle Research Development, Llc Ultra-fast nucleic acid sequencing device and a method for making and using the same
US8232582B2 (en) * 2000-04-24 2012-07-31 Life Technologies Corporation Ultra-fast nucleic acid sequencing device and a method for making and using the same
US7001792B2 (en) 2000-04-24 2006-02-21 Eagle Research & Development, Llc Ultra-fast nucleic acid sequencing device and a method for making and using the same
US20020127855A1 (en) * 2001-01-04 2002-09-12 Sauer Jon Robert Method for fabricating a pattern in a mask on a surface of an object and product manufactured thereby
US6605519B2 (en) 2001-05-02 2003-08-12 Unaxis Usa, Inc. Method for thin film lift-off processes using lateral extended etching masks and device
DE10330838B4 (de) 2003-07-08 2005-08-25 Infineon Technologies Ag Elektronisches Bauelement mit Schutzring
KR20100009625A (ko) * 2008-05-30 2010-01-28 캐논 아네르바 가부시키가이샤 규소 화합물 형성 방법 및 이의 시스템
US9847233B2 (en) * 2014-07-29 2017-12-19 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and formation thereof

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3799777A (en) * 1972-06-20 1974-03-26 Westinghouse Electric Corp Micro-miniature electronic components by double rejection
US3863330A (en) * 1973-08-02 1975-02-04 Motorola Inc Self-aligned double-diffused MOS devices
US3966577A (en) * 1973-08-27 1976-06-29 Trw Inc. Dielectrically isolated semiconductor devices
US3846822A (en) * 1973-10-05 1974-11-05 Bell Telephone Labor Inc Methods for making field effect transistors
US4124933A (en) * 1974-05-21 1978-11-14 U.S. Philips Corporation Methods of manufacturing semiconductor devices
JPS5131186A (2) * 1974-09-11 1976-03-17 Hitachi Ltd
US4037307A (en) * 1975-03-21 1977-07-26 Bell Telephone Laboratories, Incorporated Methods for making transistor structures
US4063992A (en) * 1975-05-27 1977-12-20 Fairchild Camera And Instrument Corporation Edge etch method for producing narrow openings to the surface of materials
US4026740A (en) * 1975-10-29 1977-05-31 Intel Corporation Process for fabricating narrow polycrystalline silicon members
JPS5324277A (en) * 1976-08-18 1978-03-06 Nec Corp Semiconductor devic e and its production
US4103415A (en) * 1976-12-09 1978-08-01 Fairchild Camera And Instrument Corporation Insulated-gate field-effect transistor with self-aligned contact hole to source or drain
JPS53132275A (en) * 1977-04-25 1978-11-17 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its production
US4139442A (en) * 1977-09-13 1979-02-13 International Business Machines Corporation Reactive ion etching method for producing deep dielectric isolation in silicon
JPS5444483A (en) * 1977-09-14 1979-04-07 Matsushita Electric Ind Co Ltd Mos type semiconductor device and its manufacture
US4160991A (en) * 1977-10-25 1979-07-10 International Business Machines Corporation High performance bipolar device and method for making same

Also Published As

Publication number Publication date
IT7926807A0 (it) 1979-10-26
IT1164517B (it) 1987-04-15
JPS5563827A (en) 1980-05-14
JPS57184249A (en) 1982-11-12
EP0010624B1 (de) 1982-06-23
EP0010624A1 (de) 1980-05-14
JPS5857902B2 (ja) 1983-12-22
DE2963174D1 (en) 1982-08-12
JPH0358173B2 (2) 1991-09-04
US4209349A (en) 1980-06-24

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