CA2045338A1 - Circuit de restitution de signaux d'horloge dote d'un estimateur de phase en boucle ouverte et d'une boucle a asservissement de phase a large bande - Google Patents
Circuit de restitution de signaux d'horloge dote d'un estimateur de phase en boucle ouverte et d'une boucle a asservissement de phase a large bandeInfo
- Publication number
- CA2045338A1 CA2045338A1 CA2045338A CA2045338A CA2045338A1 CA 2045338 A1 CA2045338 A1 CA 2045338A1 CA 2045338 A CA2045338 A CA 2045338A CA 2045338 A CA2045338 A CA 2045338A CA 2045338 A1 CA2045338 A1 CA 2045338A1
- Authority
- CA
- Canada
- Prior art keywords
- clock
- phase
- detected
- loop
- orthogonal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/007—Detection of the synchronisation error by features other than the received signal transition detection of error based on maximum signal power, e.g. peak value, maximizing autocorrelation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
- H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2168846A JPH0720143B2 (ja) | 1990-06-26 | 1990-06-26 | クロック同期方式 |
| JP2-168846 | 1990-06-26 | ||
| JP2-168847 | 1990-06-26 | ||
| JP2168847A JPH0720144B2 (ja) | 1990-06-26 | 1990-06-26 | クロック同期方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2045338A1 true CA2045338A1 (fr) | 1991-12-27 |
| CA2045338C CA2045338C (fr) | 1995-07-04 |
Family
ID=26492392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002045338A Expired - Fee Related CA2045338C (fr) | 1990-06-26 | 1991-06-25 | Circuit de restitution de signaux d'horloge dote d'un estimateur de phase en boucle ouverte et d'une boucle a asservissement de phase a large bande |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5235622A (fr) |
| AU (1) | AU643296B2 (fr) |
| CA (1) | CA2045338C (fr) |
| GB (1) | GB2246036B (fr) |
Families Citing this family (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3134426B2 (ja) * | 1991-11-29 | 2001-02-13 | 日本電気株式会社 | シンボル同期回路 |
| FR2692420A1 (fr) * | 1992-06-11 | 1993-12-17 | Sgs Thomson Microelectronics | Procédé et dispositif d'asservissement en fréquence et phase d'un oscillateur. |
| US5376894A (en) * | 1992-12-31 | 1994-12-27 | Pacific Communication Sciences, Inc. | Phase estimation and synchronization using a PSK demodulator |
| JPH06284159A (ja) * | 1993-03-29 | 1994-10-07 | Toshiba Corp | ディジタル復調器 |
| KR100322690B1 (ko) * | 1994-06-30 | 2002-06-20 | 윤종용 | 디지탈타이밍복원회로 |
| US5444420A (en) * | 1994-09-29 | 1995-08-22 | Harris Corporation | Numerically controlled phase lock loop synthesizer/modulator and method |
| JP3286885B2 (ja) * | 1995-11-07 | 2002-05-27 | 三菱電機株式会社 | タイミング再生手段及びダイバーシティ通信装置 |
| GB2310116B (en) * | 1996-02-08 | 2000-06-07 | Nokia Mobile Phones Ltd | Method and apparatus for clock recovery |
| US6289064B1 (en) * | 1996-03-07 | 2001-09-11 | Matsushita Communication Industrial Co., Ltd. | Synchronization equipment |
| US6044122A (en) * | 1997-01-23 | 2000-03-28 | Ericsson, Inc. | Digital phase acquisition with delay locked loop |
| US6122336A (en) * | 1997-09-11 | 2000-09-19 | Lsi Logic Corporation | Digital clock recovery circuit with phase interpolation |
| JP3504119B2 (ja) * | 1997-09-12 | 2004-03-08 | 三菱電機株式会社 | 復調装置、クロック再生装置、復調方法及びクロック再生方法 |
| JP3286907B2 (ja) * | 1997-10-30 | 2002-05-27 | 三菱電機株式会社 | タイミング位相同期検出回路及び復調器 |
| US6128357A (en) * | 1997-12-24 | 2000-10-03 | Mitsubishi Electric Information Technology Center America, Inc (Ita) | Data receiver having variable rate symbol timing recovery with non-synchronized sampling |
| JP3908033B2 (ja) * | 1999-06-04 | 2007-04-25 | 三菱電機株式会社 | 位相検出装置、これを用いたタイミング再生装置、および、これを用いた復調装置 |
| JP4366808B2 (ja) * | 2000-01-31 | 2009-11-18 | ソニー株式会社 | タイミングエラー検出回路および復調回路とその方法 |
| JP3792098B2 (ja) * | 2000-03-17 | 2006-06-28 | 三菱電機株式会社 | タイミング再生装置、これを用いた復調装置およびタイミング再生方法 |
| TW563318B (en) * | 2002-05-20 | 2003-11-21 | Via Optical Solution Inc | Timing recovery circuit and method |
| GB2409604B (en) * | 2003-12-22 | 2006-02-08 | Toshiba Res Europ Ltd | Method and apparatus for recovering timing in packet based wireless network. |
| DE102005041455A1 (de) * | 2005-08-31 | 2007-03-15 | Abb Patent Gmbh | Automatisierungstechnische Einrichtung |
| DE102005043481A1 (de) * | 2005-09-13 | 2007-03-15 | Abb Patent Gmbh | Automatisierungstechnische Einrichtung |
| DE102005043482A1 (de) * | 2005-09-13 | 2007-03-15 | Abb Patent Gmbh | Automatisierungstechnische Einrichtung |
| DE102005043487A1 (de) * | 2005-09-13 | 2007-03-15 | Abb Patent Gmbh | Automatisierungstechnische Einrichtung |
| DE102005043485A1 (de) * | 2005-09-13 | 2007-03-15 | Abb Patent Gmbh | Automatisierungstechnische Einrichtung |
| US20070139159A1 (en) * | 2005-12-15 | 2007-06-21 | Intelleflex Corporation | Clock generation circuit |
| US9154256B2 (en) * | 2013-07-22 | 2015-10-06 | Infinera Corporation | Clock phase detection in the frequency domain |
| US11757458B1 (en) * | 2022-03-11 | 2023-09-12 | Cadence Design Systems, Inc. | Digital phase-locked loop circuit |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4015083A (en) * | 1975-08-25 | 1977-03-29 | Bell Telephone Laboratories, Incorporated | Timing recovery circuit for digital data |
| US4516079A (en) * | 1983-02-09 | 1985-05-07 | Westinghouse Electric Corp. | Coherent phase shift keyed demodulator for power line communication systems |
| DE3432313A1 (de) * | 1984-09-03 | 1986-03-13 | Philips Patentverwaltung Gmbh, 2000 Hamburg | Schaltungsanordnung zum synchronisieren eines signals |
| JPS63120538A (ja) * | 1986-11-08 | 1988-05-24 | Nec Corp | タイミング再生回路 |
| GB8800739D0 (en) * | 1988-01-13 | 1988-02-10 | Ncr Co | Multipoint modem system having fast synchronization |
| DE3879202D1 (de) * | 1988-08-30 | 1993-04-15 | Siemens Ag | Verfahren und schaltungsanordnung fuer eine digitale regelung der phase von abtasttaktimpulsen. |
-
1991
- 1991-06-25 CA CA002045338A patent/CA2045338C/fr not_active Expired - Fee Related
- 1991-06-25 US US07/720,929 patent/US5235622A/en not_active Expired - Fee Related
- 1991-06-26 AU AU79343/91A patent/AU643296B2/en not_active Ceased
- 1991-06-26 GB GB9113742A patent/GB2246036B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| AU7934391A (en) | 1992-01-02 |
| CA2045338C (fr) | 1995-07-04 |
| GB2246036A (en) | 1992-01-15 |
| GB2246036B (en) | 1993-09-22 |
| GB9113742D0 (en) | 1991-08-14 |
| US5235622A (en) | 1993-08-10 |
| AU643296B2 (en) | 1993-11-11 |
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| JPS62160821A (ja) | バ−スト信号用pll回路 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |