DK2005303T3 - Hukommelseskredsløbssystem samt - fremgangsmåde - Google Patents

Hukommelseskredsløbssystem samt - fremgangsmåde

Info

Publication number
DK2005303T3
DK2005303T3 DK07750307.6T DK07750307T DK2005303T3 DK 2005303 T3 DK2005303 T3 DK 2005303T3 DK 07750307 T DK07750307 T DK 07750307T DK 2005303 T3 DK2005303 T3 DK 2005303T3
Authority
DK
Denmark
Prior art keywords
memory
circuits
interface circuit
host system
circuit
Prior art date
Application number
DK07750307.6T
Other languages
English (en)
Inventor
Suresh Natarajan Rajan
Michael John Sebastian Smith
Keith R Schakel
Frederick Daniel Weber
David T Wang
Original Assignee
Google Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/461,437 external-priority patent/US8077535B2/en
Priority claimed from US11/702,960 external-priority patent/US20080126690A1/en
Priority claimed from US11/702,981 external-priority patent/US8089795B2/en
Application filed by Google Inc filed Critical Google Inc
Priority claimed from PCT/US2007/003460 external-priority patent/WO2007095080A2/en
Application granted granted Critical
Publication of DK2005303T3 publication Critical patent/DK2005303T3/da

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Debugging And Monitoring (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DK07750307.6T 2006-02-09 2007-02-08 Hukommelseskredsløbssystem samt - fremgangsmåde DK2005303T3 (da)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US77241406P 2006-02-09 2006-02-09
US11/461,437 US8077535B2 (en) 2006-07-31 2006-07-31 Memory refresh apparatus and method
US86562406P 2006-11-13 2006-11-13
US11/702,960 US20080126690A1 (en) 2006-02-09 2007-02-05 Memory module with memory stack
US11/702,981 US8089795B2 (en) 2006-02-09 2007-02-05 Memory module with memory stack and interface with enhanced capabilities
PCT/US2007/003460 WO2007095080A2 (en) 2006-02-09 2007-02-08 Memory circuit system and method

Publications (1)

Publication Number Publication Date
DK2005303T3 true DK2005303T3 (da) 2012-07-23

Family

ID=40028972

Family Applications (3)

Application Number Title Priority Date Filing Date
DK11194883.2T DK2458505T3 (da) 2006-02-09 2007-02-08 Hukommelseskredsløbssystem og fremgangsmåde
DK07750307.6T DK2005303T3 (da) 2006-02-09 2007-02-08 Hukommelseskredsløbssystem samt - fremgangsmåde
DK13191794.0T DK2696290T3 (da) 2006-02-09 2007-02-08 Hukommelseskredsløbssystem og -metode

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DK11194883.2T DK2458505T3 (da) 2006-02-09 2007-02-08 Hukommelseskredsløbssystem og fremgangsmåde

Family Applications After (1)

Application Number Title Priority Date Filing Date
DK13191794.0T DK2696290T3 (da) 2006-02-09 2007-02-08 Hukommelseskredsløbssystem og -metode

Country Status (6)

Country Link
EP (7) EP2450798B1 (da)
JP (3) JP5205280B2 (da)
KR (3) KR101429869B1 (da)
AT (1) ATE554447T1 (da)
DK (3) DK2458505T3 (da)
HK (1) HK1250270A1 (da)

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Also Published As

Publication number Publication date
KR101404926B1 (ko) 2014-06-10
EP2005303B1 (en) 2012-04-18
EP2458505B1 (en) 2014-10-08
JP2013012232A (ja) 2013-01-17
DK2696290T3 (da) 2016-02-15
EP2458505A1 (en) 2012-05-30
HK1250270A1 (en) 2018-12-07
EP2696290A1 (en) 2014-02-12
EP2450800A1 (en) 2012-05-09
EP2005303A4 (en) 2009-09-16
EP3276495A1 (en) 2018-01-31
KR101343252B1 (ko) 2013-12-18
EP2450798B1 (en) 2013-10-30
JP2009526323A (ja) 2009-07-16
JP5730251B2 (ja) 2015-06-03
EP2706461A1 (en) 2014-03-12
DK2458505T3 (da) 2014-12-01
EP2005303A2 (en) 2008-12-24
JP5205280B2 (ja) 2013-06-05
KR20130141693A (ko) 2013-12-26
JP2013012233A (ja) 2013-01-17
JP5730252B2 (ja) 2015-06-03
KR20140056349A (ko) 2014-05-09
EP2450800B1 (en) 2014-04-23
EP2696290B1 (en) 2015-12-23
KR101429869B1 (ko) 2014-08-12
EP2450798A1 (en) 2012-05-09
KR20080108975A (ko) 2008-12-16
ATE554447T1 (de) 2012-05-15

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