EE200200261A - Meetod räninanostruktuuri, ränikvantviikude massiivi ning sellel baseeruvate komponentide formeerimiseks - Google Patents

Meetod räninanostruktuuri, ränikvantviikude massiivi ning sellel baseeruvate komponentide formeerimiseks

Info

Publication number
EE200200261A
EE200200261A EEP200200261A EEP200200261A EE200200261A EE 200200261 A EE200200261 A EE 200200261A EE P200200261 A EEP200200261 A EE P200200261A EE P200200261 A EEP200200261 A EE P200200261A EE 200200261 A EE200200261 A EE 200200261A
Authority
EE
Estonia
Prior art keywords
silicon
array
forming
components based
nanostructure
Prior art date
Application number
EEP200200261A
Other languages
English (en)
Estonian (et)
Inventor
K. Smirnov Valery
S. Kibalov Dmitri
Original Assignee
Sceptre Electronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sceptre Electronics Limited filed Critical Sceptre Electronics Limited
Publication of EE200200261A publication Critical patent/EE200200261A/xx

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/014—Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/812—Single quantum well structures
    • H10D62/813—Quantum wire structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Physical Vapour Deposition (AREA)
  • Thin Film Transistor (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Drying Of Semiconductors (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
EEP200200261A 1999-11-25 2000-10-02 Meetod räninanostruktuuri, ränikvantviikude massiivi ning sellel baseeruvate komponentide formeerimiseks EE200200261A (et)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
RU99124768/28A RU2173003C2 (ru) 1999-11-25 1999-11-25 Способ образования кремниевой наноструктуры, решетки кремниевых квантовых проводков и основанных на них устройств
PCT/IB2000/001397 WO2001039259A1 (en) 1999-11-25 2000-10-02 Methods of formation of a silicon nanostructure, a silicon quantum wire array and devices based thereon

Publications (1)

Publication Number Publication Date
EE200200261A true EE200200261A (et) 2003-08-15

Family

ID=20227346

Family Applications (1)

Application Number Title Priority Date Filing Date
EEP200200261A EE200200261A (et) 1999-11-25 2000-10-02 Meetod räninanostruktuuri, ränikvantviikude massiivi ning sellel baseeruvate komponentide formeerimiseks

Country Status (23)

Country Link
US (1) US6274007B1 (cs)
EP (1) EP1104011A1 (cs)
JP (1) JP2001156050A (cs)
KR (1) KR20020069195A (cs)
CN (1) CN1399791A (cs)
AU (1) AU7547400A (cs)
BG (1) BG106739A (cs)
BR (1) BR0016095A (cs)
CA (1) CA2392307A1 (cs)
CZ (1) CZ20021824A3 (cs)
EE (1) EE200200261A (cs)
HR (1) HRP20020459A2 (cs)
HU (1) HUP0203517A2 (cs)
IL (1) IL149832A0 (cs)
IS (1) IS6393A (cs)
MX (1) MXPA02005281A (cs)
NO (1) NO20022427L (cs)
PL (1) PL355890A1 (cs)
RU (1) RU2173003C2 (cs)
SK (1) SK7442002A3 (cs)
WO (1) WO2001039259A1 (cs)
YU (1) YU38202A (cs)
ZA (1) ZA200204822B (cs)

Families Citing this family (112)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2191444C1 (ru) * 2001-10-09 2002-10-20 Общество с ограниченной ответственностью "Агентство маркетинга научных разработок" Способ изготовления полевого транзистора с периодически легированным каналом
US6872645B2 (en) * 2002-04-02 2005-03-29 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
RU2204179C1 (ru) * 2002-08-19 2003-05-10 Общество с ограниченной ответственностью "Агентство маркетинга научных разработок" Способ формирования нанорельефа на поверхности пленок
RU2214359C1 (ru) * 2002-09-05 2003-10-20 Санкт-Петербургский государственный институт точной механики и оптики (технический университет) Способ формирования решетки нанокластеров кремния на структурированной подложке
US7067867B2 (en) * 2002-09-30 2006-06-27 Nanosys, Inc. Large-area nonenabled macroelectronic substrates and uses therefor
US7051945B2 (en) * 2002-09-30 2006-05-30 Nanosys, Inc Applications of nano-enabled large area macroelectronic substrates incorporating nanowires and nanowire composites
US7619562B2 (en) * 2002-09-30 2009-11-17 Nanosys, Inc. Phased array systems
JP4669784B2 (ja) * 2002-09-30 2011-04-13 ナノシス・インコーポレイテッド ナノワイヤトランジスタを用いる集積ディスプレイ
US7135728B2 (en) * 2002-09-30 2006-11-14 Nanosys, Inc. Large-area nanoenabled macroelectronic substrates and uses therefor
EP1547139A4 (en) 2002-09-30 2009-08-26 Nanosys Inc LARGE AREA, NANO-READY MACROELECTRONIC SUBSTRATES AND USES THEREOF
RU2212375C1 (ru) * 2002-11-04 2003-09-20 Фонд развития новых медицинских технологий "АЙРЭС" Способ получения тонких пленок с фрактальной структурой
US20060273299A1 (en) * 2003-06-26 2006-12-07 Rj Mears, Llc Method for making a semiconductor device including a dopant blocking superlattice
US20060220118A1 (en) * 2003-06-26 2006-10-05 Rj Mears, Llc Semiconductor device including a dopant blocking superlattice
US7531829B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7153763B2 (en) 2003-06-26 2006-12-26 Rj Mears, Llc Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
US20070063185A1 (en) * 2003-06-26 2007-03-22 Rj Mears, Llc Semiconductor device including a front side strained superlattice layer and a back side stress layer
US20060243964A1 (en) * 2003-06-26 2006-11-02 Rj Mears, Llc Method for making a semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US7598515B2 (en) * 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US7586165B2 (en) * 2003-06-26 2009-09-08 Mears Technologies, Inc. Microelectromechanical systems (MEMS) device including a superlattice
US20050282330A1 (en) * 2003-06-26 2005-12-22 Rj Mears, Llc Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layers
US7045813B2 (en) * 2003-06-26 2006-05-16 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US7229902B2 (en) * 2003-06-26 2007-06-12 Rj Mears, Llc Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US20050279991A1 (en) * 2003-06-26 2005-12-22 Rj Mears, Llc Semiconductor device including a superlattice having at least one group of substantially undoped layers
US7535041B2 (en) * 2003-06-26 2009-05-19 Mears Technologies, Inc. Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US20060267130A1 (en) * 2003-06-26 2006-11-30 Rj Mears, Llc Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween
US7227174B2 (en) * 2003-06-26 2007-06-05 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7033437B2 (en) * 2003-06-26 2006-04-25 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US7491587B2 (en) * 2003-06-26 2009-02-17 Mears Technologies, Inc. Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
US7531850B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a memory cell with a negative differential resistance (NDR) device
US6830964B1 (en) * 2003-06-26 2004-12-14 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US7586116B2 (en) * 2003-06-26 2009-09-08 Mears Technologies, Inc. Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US7659539B2 (en) 2003-06-26 2010-02-09 Mears Technologies, Inc. Semiconductor device including a floating gate memory cell with a superlattice channel
US20070015344A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US20040266116A1 (en) * 2003-06-26 2004-12-30 Rj Mears, Llc Methods of fabricating semiconductor structures having improved conductivity effective mass
US20070020833A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
US20060292765A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc Method for Making a FINFET Including a Superlattice
US20070020860A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
US7045377B2 (en) * 2003-06-26 2006-05-16 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US20060231857A1 (en) * 2003-06-26 2006-10-19 Rj Mears, Llc Method for making a semiconductor device including a memory cell with a negative differential resistance (ndr) device
US20060011905A1 (en) * 2003-06-26 2006-01-19 Rj Mears, Llc Semiconductor device comprising a superlattice dielectric interface layer
US20060289049A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer
US7514328B2 (en) * 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
US20070010040A1 (en) * 2003-06-26 2007-01-11 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
US7612366B2 (en) * 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US7531828B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US7202494B2 (en) * 2003-06-26 2007-04-10 Rj Mears, Llc FINFET including a superlattice
US20040262594A1 (en) * 2003-06-26 2004-12-30 Rj Mears, Llc Semiconductor structures having improved conductivity effective mass and methods for fabricating same
US7446002B2 (en) * 2003-06-26 2008-11-04 Mears Technologies, Inc. Method for making a semiconductor device comprising a superlattice dielectric interface layer
US20070063186A1 (en) * 2003-06-26 2007-03-22 Rj Mears, Llc Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layer
WO2005018005A1 (en) * 2003-06-26 2005-02-24 Rj Mears, Llc Semiconductor device including mosfet having band-engineered superlattice
RU2250535C1 (ru) * 2003-08-14 2005-04-20 Институт физики полупроводников Объединенного института физики полупроводников СО РАН Полевой нанотранзистор
US7768018B2 (en) 2003-10-10 2010-08-03 Wostec, Inc. Polarizer based on a nanowire grid
RU2240280C1 (ru) * 2003-10-10 2004-11-20 Ворлд Бизнес Ассошиэйтс Лимитед Способ формирования упорядоченных волнообразных наноструктур (варианты)
DE10351059B4 (de) * 2003-10-31 2007-03-01 Roth & Rau Ag Verfahren und Vorrichtung zur Ionenstrahlbearbeitung von Oberflächen
US7211844B2 (en) * 2004-01-29 2007-05-01 International Business Machines Corporation Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage
US20050167655A1 (en) * 2004-01-29 2005-08-04 International Business Machines Corporation Vertical nanotube semiconductor device structures and methods of forming the same
US8025960B2 (en) * 2004-02-02 2011-09-27 Nanosys, Inc. Porous substrates, articles, systems and compositions comprising nanofibers and methods of their use and production
US7553371B2 (en) 2004-02-02 2009-06-30 Nanosys, Inc. Porous substrates, articles, systems and compositions comprising nanofibers and methods of their use and production
US20110039690A1 (en) * 2004-02-02 2011-02-17 Nanosys, Inc. Porous substrates, articles, systems and compositions comprising nanofibers and methods of their use and production
US20050279274A1 (en) * 2004-04-30 2005-12-22 Chunming Niu Systems and methods for nanowire growth and manufacturing
CA2564220A1 (en) * 2004-04-30 2005-12-15 Nanosys, Inc. Systems and methods for nanowire growth and harvesting
US7785922B2 (en) 2004-04-30 2010-08-31 Nanosys, Inc. Methods for oriented growth of nanowires on patterned substrates
JP2008506254A (ja) * 2004-07-07 2008-02-28 ナノシス・インコーポレイテッド ナノワイヤーの集積及び組み込みのためのシステムおよび方法
WO2006124055A2 (en) * 2004-10-12 2006-11-23 Nanosys, Inc. Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires
US7473943B2 (en) * 2004-10-15 2009-01-06 Nanosys, Inc. Gate configuration for nanowire electronic devices
RU2267832C1 (ru) * 2004-11-17 2006-01-10 Александр Викторович Принц Способ изготовления микро- и наноприборов на локальных подложках
JP5305658B2 (ja) * 2004-11-24 2013-10-02 ナノシス・インク． ナノワイヤに注入されたドーパントイオンの活性化方法
JP2008522226A (ja) * 2004-11-30 2008-06-26 アグーラ テクノロジーズ インコーポレイテッド 大規模ワイヤ・グリッド偏光子の応用および作製技術
US7351346B2 (en) * 2004-11-30 2008-04-01 Agoura Technologies, Inc. Non-photolithographic method for forming a wire grid polarizer for optical and infrared wavelengths
US7560366B1 (en) 2004-12-02 2009-07-14 Nanosys, Inc. Nanowire horizontal growth and substrate removal
KR100624461B1 (ko) * 2005-02-25 2006-09-19 삼성전자주식회사 나노 와이어 및 그 제조 방법
US7604690B2 (en) * 2005-04-05 2009-10-20 Wostec, Inc. Composite material for ultra thin membranes
WO2007038164A2 (en) * 2005-09-23 2007-04-05 Nanosys, Inc. Methods for nanostructure doping
RU2300158C1 (ru) * 2005-09-29 2007-05-27 Институт микроэлектроники и информатики РАН Способ формирования субмикронной и нанометровой структуры
US7517702B2 (en) * 2005-12-22 2009-04-14 Mears Technologies, Inc. Method for making an electronic device including a poled superlattice having a net electrical dipole moment
TW200733379A (en) * 2005-12-22 2007-09-01 Mears R J Llc Electronic device including a poled superlattice having a net electrical dipole moment
US7741197B1 (en) 2005-12-29 2010-06-22 Nanosys, Inc. Systems and methods for harvesting and reducing contamination in nanowires
US7951422B2 (en) * 2005-12-29 2011-05-31 Nanosys, Inc. Methods for oriented growth of nanowires on patterned substrates
WO2007098138A2 (en) * 2006-02-21 2007-08-30 Mears Technologies, Inc. Semiconductor device comprising a lattice matching layer and associated methods
FI122010B (fi) * 2006-08-09 2011-07-15 Konstantin Arutyunov Ionisuihkuetsausmenetelmä ja -laitteisto
US7776760B2 (en) * 2006-11-07 2010-08-17 Nanosys, Inc. Systems and methods for nanowire growth
KR100836426B1 (ko) * 2006-11-24 2008-06-09 삼성에스디아이 주식회사 비휘발성 메모리 소자 및 그 제조방법과 이를 포함한메모리 장치
US7786024B2 (en) * 2006-11-29 2010-08-31 Nanosys, Inc. Selective processing of semiconductor nanowires by polarized visible radiation
US20080129930A1 (en) * 2006-12-01 2008-06-05 Agoura Technologies Reflective polarizer configuration for liquid crystal displays
US7781827B2 (en) 2007-01-24 2010-08-24 Mears Technologies, Inc. Semiconductor device with a vertical MOSFET including a superlattice and related methods
US7928425B2 (en) * 2007-01-25 2011-04-19 Mears Technologies, Inc. Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
US7880161B2 (en) 2007-02-16 2011-02-01 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
US7863066B2 (en) * 2007-02-16 2011-01-04 Mears Technologies, Inc. Method for making a multiple-wavelength opto-electronic device including a superlattice
US7812339B2 (en) * 2007-04-23 2010-10-12 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures
US8668833B2 (en) * 2008-05-21 2014-03-11 Globalfoundries Singapore Pte. Ltd. Method of forming a nanostructure
HUE054466T2 (hu) * 2009-05-19 2021-09-28 Oned Mat Inc Nanoszerkezetû anyagok akkumulátor alkalmazásokhoz
US8623288B1 (en) 2009-06-29 2014-01-07 Nanosys, Inc. Apparatus and methods for high density nanowire growth
CN102386096A (zh) * 2010-08-31 2012-03-21 上海华虹Nec电子有限公司 改善ldmos性能一致性和稳定性的方法
WO2013006077A1 (en) * 2011-07-06 2013-01-10 Wostec, Inc. Solar cell with nanostructured layer and methods of making and using
EP2740162B1 (en) 2011-08-05 2019-07-03 Wostec, Inc. Light emitting diode with nanostructured layer, method of making a light emitting diode and nanomask used in the method.
WO2013089578A1 (en) * 2011-12-12 2013-06-20 Wostec, Inc. Sers-sensor with nanostructured surface and methods of making and using
WO2013109157A1 (en) 2012-01-18 2013-07-25 Wostec, Inc. Arrangements with pyramidal features having at least one nanostructured surface and methods of making and using
WO2013141740A1 (en) 2012-03-23 2013-09-26 Wostec, Inc. Sers-sensor with nanostructured layer and methods of making and using
WO2014142700A1 (en) 2013-03-13 2014-09-18 Wostec Inc. Polarizer based on a nanowire grid
CN106104805B (zh) 2013-11-22 2020-06-16 阿托梅拉公司 包括超晶格穿通停止层堆叠的垂直半导体装置和相关方法
WO2015077580A1 (en) 2013-11-22 2015-05-28 Mears Technologies, Inc. Semiconductor devices including superlattice depletion layer stack and related methods
US9716147B2 (en) 2014-06-09 2017-07-25 Atomera Incorporated Semiconductor devices with enhanced deterministic doping and related methods
WO2015199573A1 (en) * 2014-06-26 2015-12-30 Wostec, Inc. Wavelike hard nanomask on a topographic feature and methods of making and using
US9722046B2 (en) 2014-11-25 2017-08-01 Atomera Incorporated Semiconductor device including a superlattice and replacement metal gate structure and related methods
WO2016187038A1 (en) 2015-05-15 2016-11-24 Atomera Incorporated Semiconductor devices with superlattice and punch-through stop (pts) layers at different depths and related methods
WO2016196600A1 (en) 2015-06-02 2016-12-08 Atomera Incorporated Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
US9558939B1 (en) 2016-01-15 2017-01-31 Atomera Incorporated Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source
US10672427B2 (en) 2016-11-18 2020-06-02 Wostec, Inc. Optical memory devices using a silicon wire grid polarizer and methods of making and using
WO2018156042A1 (en) 2017-02-27 2018-08-30 Wostec, Inc. Nanowire grid polarizer on a curved surface and methods of making and using
RU2671294C1 (ru) * 2017-11-28 2018-10-30 Федеральное государственное бюджетное образовательное учреждение высшего образования "Чеченский государственный университет" Способ изготовления полупроводникового прибора
CN110137254B (zh) * 2019-04-30 2021-07-09 中国科学技术大学 半导体栅极电控量子点及其制备方法
CN114497275A (zh) * 2021-12-29 2022-05-13 昆明物理研究所 硅量子点光伏异质结制备方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2609587B2 (ja) * 1986-04-21 1997-05-14 株式会社日立製作所 半導体装置
GB8823047D0 (en) * 1988-09-30 1988-11-09 Imperial College Fabrication of semiconductor nanostructures
RU2007786C1 (ru) * 1991-06-26 1994-02-15 Физико-технический институт им.А.Ф.Иоффе РАН Бистабильный абсорбционный оптоэлектронный прибор
RU2007783C1 (ru) * 1991-10-02 1994-02-15 Борис Михайлович Овчинников Способ создания наноструктур
RU2062530C1 (ru) * 1992-03-12 1996-06-20 Борис Сергеевич Павлов Квантово-интерференционный транзистор
US5689603A (en) * 1993-07-07 1997-11-18 Huth; Gerald C. Optically interactive nanostructure
RU2141699C1 (ru) 1997-09-30 1999-11-20 Закрытое акционерное общество Центр "Анализ Веществ" Способ формирования твердотельных наноструктур

Also Published As

Publication number Publication date
CA2392307A1 (en) 2001-05-31
IL149832A0 (en) 2002-11-10
BR0016095A (pt) 2004-03-23
NO20022427D0 (no) 2002-05-22
AU7547400A (en) 2001-06-04
CZ20021824A3 (cs) 2004-10-13
YU38202A (sh) 2006-08-17
RU2173003C2 (ru) 2001-08-27
JP2001156050A (ja) 2001-06-08
SK7442002A3 (en) 2003-05-02
IS6393A (is) 2002-05-24
BG106739A (bg) 2003-08-29
MXPA02005281A (es) 2006-02-10
NO20022427L (no) 2002-06-25
EP1104011A1 (en) 2001-05-30
HUP0203517A2 (en) 2003-07-28
US6274007B1 (en) 2001-08-14
PL355890A1 (pl) 2004-05-31
KR20020069195A (ko) 2002-08-29
HRP20020459A2 (en) 2005-10-31
ZA200204822B (en) 2003-11-26
CN1399791A (zh) 2003-02-26
WO2001039259A1 (en) 2001-05-31

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